Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

 A poly-phase based interpolation filter computation involves an input-matrix and coefficient-matrix of size (P×M) each, where P is the up-sampling factor and M=N/P, N is the filter length. The input-matrix and the coefficient-matrix resizes when P changes. An analysis of interpolation filter computation for different up-sampling factors is made in ...

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

 This paper presents a fully pipelined color demosaicking design. To improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demo...

Byte-Reconfigurable LDPC Codec Design With Application to High Performance ECC of NAND Flash Memory Systems

 The reliability of NAND Flash memory deteriorates due to multi-level cell technique and advanced manufacturing technology. To deal with more errors, LDPC codes show superior performance to conventional BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chi...

Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

 Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the threshold voltage of the pMOS transistor, and...

A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)

 This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m = Dw = 3m/2 -1 multiple error combinations out of all the possible 2m - 1 errors, which is s...

Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

 In this brief, the implementation of residue number system reverse converters based on well-known regular and modular parallelprefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of pa...

Quaternary Logic Lookup Table in Standard CMOS

 Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this ...

Implementation of Sub-threshold Adiabatic Logic for Ultralow-Power Application

 Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralowpower circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schem...

An Efficient Constant Multiplier Architecture Based on Vertical Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

 This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coeffi- cients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the pr...

A Low-Power Architecture for the Design of a One-Dimensional Median Filter

 This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the s...

A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

 This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) det...

Partially Parallel Encoder Architecture for Long Polar Codes

 Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. Although the previous fully parallel encoder is intuitive and easy to implement, it is not suitable ...

Obfuscating DSP Circuits via High-Level Transformations

 This paper presents a novel approach to design obfuscated circuits for digital signal processing (DSP) applications using high-level transformations, a key-based obfuscating finite-state machine (FSM), and a reconfigurator. The goal is to design DSP circuits that are harder to reverse engineer. Highlevel transformations of iterative data-flow graph...

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

 This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed cl...

Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications

 The dedicated short-range communication (DSRC) is an emerging technique to push the intelligent transportation system into our daily life. The DSRC standards generally adopt FM0 and Manchester codes to reach dcbalance, enhancing the signal reliability. Nevertheless, the coding-diversity between the FM0 and Manchester codes seriously limits the pote...

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

 Iterative methods are basic building blocks of communication systems and often represent a dominating part of the system, and therefore, they necessitate careful design and implementation for optimal performance. In this brief, we propose a novel field programmable gate arrays design of matrix–vector multiplier that can be used to efficiently imple...

Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

 Iterative methods are basic building blocks of communication systems and often represent a dominating part of the system, and therefore, they necessitate careful design and implementation for optimal performance. In this brief, we propose a novel field programmable gate arrays design of matrix–vector multiplier that can be used to efficiently imple...

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

 We propose a low-power Content-Addressable Memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered-network using binary connections that onaverage eliminates most of the parallel comparisons performed ...

VLSI IMPLEMENTATION OF EFFICIENT IMAGE WATERMARKING ALGORITHM

 Protection and authentication of digital multimedia content during transmission has become very important with the ongoing development in communication and networking field. Aiming at this popular research topic of recent time, this paper presents a comparative analysis of different watermarking techniques performed in MATLAB. It also presents a ro...

Temporarily Fine Grained Sleep Technique for Near and Subthreshold Parallel Architectures

 This paper presents a design approach for improving energy-efficiency and throughput of parallel architectures in near- and subthreshold voltage circuits. The focus is to suppress leakage energy dissipation of the idle portions of circuits during active modes, which can allow us to wholly transform the throughput improvement from parallel architect...

Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

 The Hilbert Huang Transform (HHT) has been used extensively in the time-frequency analysis of electroencephalography (EEG) signals and Brain-Computer Interfaces. Most studies utilizing the HHT for extracting features in seizure prediction have used intracranial EEG recordings. Invasive implants in the cortex have unknown long term consequences and ...

Pre-Encoded Multipliers Based on Non-Redundant Radix-4Signed-Digit Encoding

 In this paper, we introduce an architecture of pre-encoded multipliers for Digital Signal Processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values {-1, 0, +1, +2} or {-2, -1, 0, +1}, is proposed leading to a multiplier design wi...

Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

 As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks f...

Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter withWide Cutoff Frequency Range and NarrowTransition Bandwidth

 Reconfigurable filters based on the spectral parameter approximation (SPA) technique and its combination with other techniques provide a continuous control over the cutoff frequency (fc). However, when very wide fc range and narrow transition bandwidth is desired, these filters either fail to satisfy some of the specifications or have extremely hig...

VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding

 For multiplier dominated applications such as digital signal processing, wireless communications, and computer applications, high speed multiplier designs has always been a primary requisite. In this paper a high performance 64x64 bit redundant binary (RB) multiplier have been designed by using recently proposed redundant binary encoding approach t...

RF Power Gating: A Low Power Technique for Adaptive Radios

 In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on...

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

 The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant...

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

 A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary fre...

An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2^k, 2^p-1}

 The application of residue number system (RNS) to digital signal processing lies in the ability to operate on signed numbers. However, the available RNS-to-binary (reverse) converters have been designed for unsigned numbers, which means that they do not produce signed outputs. Usually, some additional circuits are introduced at the output of the re...

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

 This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated volta...

Source Code Error Detection in High-Level Synthesis Functional Verification

 A dynamic functional verification method that compares untimed simulations versus timed simulations for synthesizable [high-level synthesis (HLS)] behavioral descriptions (ANSI-C) is presented in this paper. This paper proposes a method that automatically inserts a set of probes into the untimed behavioral description. These probes record the statu...

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

 In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cel...

Low-Power FPGA Design Using Memoization-Based Approximate Computing

 Field-programmable gate arrays (FPGAs) are increasingly used as the computing platform for fast and energyefficient execution of recognition, mining, and search applications. Approximate computing is one promising method for achieving energy efficiency. Compared with most prior works on approximate computing, which target approximate processors and...

Concept, Design, and Implementation of Reconfigurable CORDIC

 This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for circular or for hyperbolic trajectories in rotation as well as vectoring-modes. It can, therefore, be used to perform all the functions of both circular a...

Code Compression for Embedded Systems Using Separated Dictionaries

 Engineers must consider performance, power consumption, and cost when designing embedded digital systems; furthermore, memory is a key factor in such systems. Code compression is a technique used in embedded systems to reduce the memory usage. BitMask-based code compression is a modified version of dictionary-based code compression. The basic purpo...

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

 Single error correction (SEC) codes are widely used to protect data stored in memories and registers. In some applications, such as networking, a few control bits are added to the data to facilitate their processing. For example, flags to mark the start or the end of a packet are widely used. Therefore, it is important to have SEC codes that protec...

Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

 In this paper, we present a low-power, efficacious, and scalable system for the detection of symptomatic patterns in biological audio signals. The digital audio recordings of various symptoms, such as cough, sneeze, and so on, are spectrally analyzed using a discrete wavelet transform. Subsequently, we use simple mathematical metrics, such as energ...

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

 This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in firstinput firstouptput buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated ...

HDL-Based Modeling Approach for Digital Simulation of Adiabatic Quantum Flux Parametron Logic

 AQFP (adiabatic quantum-flux-parametron) circuits are currently verified by analog-based simulation, which would be an obstacle for large-scale circuits design. In this paper, we present a logic simulation model for AQFP logic. We made a functional model based on a finite-state machine approach using a hardware description language (HDL), which ena...

Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

 This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high powerdelay ...

A High speed and Power Efficient Voltage Level Shifter for Dual Supply Applications

 This brief presents a fast and power-efficient voltage levelshifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is due to the fact that not only the strength of the pull-up device is significantly reduced when the pull-down device is pulling down the o...

A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

 In this paper, a novel computation and energy reduction technique for High Efficiency Video Coding (HEVC) Discrete Cosine Transform (DCT) for all Transform Unit (TU) sizes is proposed. The proposed technique reduces the computational complexity of HEVC DCT significantly at the expense of slight decrease in PSNR and slight increase in bit rate by on...

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

 This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial point...

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

 In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing mult...

Graph-Based Transistor Network Generation Method for Super gate Design

 Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series–parallel (SP) and non-SP switch arrangements, imp...

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

 Hardware acceleration has been proved an extremely promising implementation strategy for the digital signal processing (DSP) domain. Rather than adopting a monolithic application-specific integrated circuit design approach, in this brief, we present a novel accelerator architecture comprising flexible computational units that support the execution ...

A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography

 This paper presents a fixed-point reconfigurable parallel VLSI hardware architecture for real-time Electrical Capacitance Tomography (ECT). It is modular and consists of a front-end module which performs precise capacitance measurements in a time multiplexed manner using Capacitance to Digital Converter (CDC) technique. Another FPGA module performs...

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

 Transpose-form finite impulse response (FIR) structures are inherently pipelined and support multiple constant multiplication (MCM) results in significant saving of computation. However, transpose-form configuration does not directly support the block processing unlike direct-form configuration. In this paper, we explore the possibility of realizat...

Pre-charge-Free, Low-Power Content-Addressable Memory

 Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. Parallel NOR- and NAND-type matchline (ML) CAMs are suitable for high-search-speed and low-power-consumption applications, respectively. The NOR-type ML CAM require...

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

 A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition...

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control

 A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored contents rather than addresses. The additional don’t care (X) state makes the TCAM suitable for many network applications but the large amount of cell requirement for storage consumes high power and takes a large design area. This p...

A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications

 Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adap...

A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC

 Inverter-based implementation of operational transconductance amplifiers is an attractive approach for low voltage realization of analog subsystems. However, the high sensitivity of inverter like amplifiers’ performance to process and temperature variations limit the achievable performance of the whole system across process and temperature corners....

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

 Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large a...

Probability Driven Multi bit Flip-Flop Integration with Clock Gating

 Data-driven clock gated (DDCG) and multibit flip-flops (MBFFs) are two low-power design techniques that are usually treated separately. Combining these techniques into a single grouping algorithm and design flow enables further power savings. We study MBFF multiplicity and its synergy with FF data-to-clock toggling probabilities. A probabilistic mo...

Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

 Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a lo...

Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM

 Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. Th...

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

 Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and ease of scaling with process technology. However, their use in many applications is limited due to poor phase noise and jitter performance. Thermal noise and flicker noise contribute jitter that decreases inversely with oscillation frequency. This paper...

Designing Tunable Sub-threshold Logic Circuits Using Adaptive Feedback Equalization

 Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to an order of magnitude variations in ION/IOFF ratios leadi...

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

  This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDL...

OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

 In this paper, a new design procedure has been proposed for realization of logarithmic function via three phases: 1) differentiation; 2) division; and 3) integration for any arbitrary analog signal. All the basic building blocks, i.e., differentiator, divider, and integrator, are realized by operational transconductance amplifier, a current mode de...

Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

 A method is proposed to detect failing cells due to bias temperature instability (BTI) in Static Random Access Memories (SRAMs) en route to failure. If potentially failing cells are detected prior to failure, SRAMs can be operated without failures, since the detection of potentially failing cells can trigger reconfiguration, given available memory ...

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

 The previously proposed average-8T static random access memory (SRAM) has a competitive area and does not require a write-back scheme. In the case of an average-8T SRAM architecture, a full-swing local bitline (BL) that is connected to the gate of the read buffer can be achieved with a boosted wordline (WL) voltage. However, in the case of an avera...

A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

 This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS pr...

A Fault Tolerance Technique for Combinational Circuits Based on Selective Transistor Redundance

 With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. This paper is focused on designing combinational circuits for soft error tolerance with minimal area overhead. The idea is based on analyzing random pattern testability of faults in a circuit and prote...

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

 A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from ...

Gate Diffusion input based 4-bit Vedic Multiplier Design

 A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CM...

Energy Efficient TCAM Search Engine Design Using Priority Decision in Memory Technology

 Ternary content-addressable memory (TCAM)-based search engines generally need a priority encoder (PE) to select the highest priority match entry for resolving the multiple match problem due to the don’t care (X) features of TCAM. In contemporary network security, TCAM-based search engines are widely used in regular expression matching across multip...

Efficient Super Resolution Algorithm using Overlapping Bicubic Interpolation

 In practical CCTV applications, there are problems of the camera with low resolution, camera fields of view, and lighting environments. These could degrade the image quality and it is difficult to extract useful information for further processing. Super-resolution techniques have been proposed widely by the researchers. However, many approaches are...

A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell

 A novel 8-transistor (8T) static random access memory cell with improved data stability in subthreshold operation is designed. The proposed single-ended with dynamic feedback control 8T static RAM (SRAM) cell enhances the static noise margin (SNM) for ultralow power supply. It achieves write SNM of 1.4× and 1.28× as that of isoarea 6T and read-deco...

A Real Time FHD Learning Based Super Resolution System Without a Frame Buffer

 This brief presents a real-time learning-based superresolution (SR) system without a frame buffer. The system running on an Altera Stratix IV field programmable gate array can achieve output resolution of 1920 × 1080 (FHD) at 60 fps. The proposed architecture performs an anchored neighborhood regression algorithm that generates a high-resolution im...

A Closed Form Expression for Minimum Operating Voltage of CMOS D Flip Flop

 In this paper, a closed-form expression for estimating the minimum operating voltage (VDDmin) of D flip-flops (FFs) is proposed. VDDmin is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that VDDmin of FFs is a linear function of the square root of logarithm of the number of FF...

Low-Complexity Methodology for Complex Square-Root Computation

 In this brief, we propose a low-complexity methodology to compute a complex square root using only a circular coordinate rotation digital computer (CORDIC) as opposed to the state-of-the-art techniques that need both circular as well as hyperbolic CORDICs. Subsequently, an architecture has been designed based on the proposed methodology and impleme...

Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology

 One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of improvement has been done in this area to refine the architecture and performance of full adder circuit design. In this paper two designs of novel ...

Energy Efficient Approximate Multiplier Design using Bit Significance Driven Logic Compression

 Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic ...

Approximate Error Detection With Stochastic Checkers

 Designing reliable systems, while eschewing the high overheads of conventional fault tolerance techniques, is a critical challenge in the deeply scaled CMOS and post-CMOS era. To address this challenge, we leverage the intrinsic resilience of application domains such as multimedia, recognition, mining, search, and analytics where acceptable outputs...

An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplication

 Parallel matrix processing is a typical operation in many systems, and in particular matrix–vector multiplication (MVM) is one of the most common operations in the modern digital signal processing and digital communication systems. This paper proposes a faulttolerant design for integer parallel MVMs. The scheme combines ideas from error correction ...

An ADPLL based PSK Receiver for VHBR 13.56 MHz Contactless Smartcards and NFC Applications

 This paper proposes an all-digital phase-locked loop (ADPLL) used as the phase-shift keying (PSK) receiver for very high bit rate (VHBR) of 13.56 MHz smartcards. A detailed implementation from system to circuit level is presented. This ADPLL-based PSK demodulator mainly consists of a high dynamic range time to digital converter (TDC) without pulse ...

Low Power Split Radix FFT Processors using Radix-2 Butterfly Units

 Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of S...

Design of Power and Area Efficient Approximate Multipliers

 Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is ...

Antiwear Leveling Design for SSDs With Hybrid ECC Capability

 With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-ra...

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability

 Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consist...

Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map

 Stochastic computing (SC) is a digital computation approach that operates on random bit streams to perform complex tasks with much smaller hardware footprints compared with conventional binary radix approaches. SC works based on the assumption that input bit streams are independent random sequences of 1s and 0s. Previous SC efforts have avoided imp...

RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing

 In this paper, we propose an approximate multiplier that is high speed yet energy efficient. The approach is to round the operands to the nearest exponent of two. This way the computational intensive part of the multiplication is omitted improving speed and energy consumption at the price of a small error. The proposed approach is applicable to bot...

Resource-Efficient SRAM-based Ternary Content Addressable Memory

 Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel m...

Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

 In this paper, we propose four 4:2 compressors, which have the flexibility of switching between the exact and approximate operating modes. In the approximate mode, these dual-quality compressors provide higher speeds and lower power consumptions at the cost of lower accuracy. Each of these compressors has its own level of accuracy in the approximat...

A Floating-Point Fused Dot-Product Unit

 A floating-point fused dot-product unit is presented that performs single-precision floating-point multiplication and addition operations on two pairs of data in a time that is only 150% the time required for a conventional floating-point multiplication. When placed and routed in a 45nm process, the fused dot-product unit occupied about 70% of the ...

Towards Efficient Modular Adders based on Reversible Circuits

 Reversible logic is a computing paradigm that has attracted significant attention in recent years due to its properties that lead to ultra-low power and reliable circuits. Reversible circuits are fundamental, for example, for quantum computing. Since addition is a fundamental operation, designing efficient adders is a cornerstone in the research of...

High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop

 Positron emission tomography (PET) is a nuclear functional imaging technique that produces a three-dimensional image of functional organs in the body. PET requires high resolution, fast and low power multichannel analog to digital converter (ADC). A typical multichannel ADC for PET scanner architecture consists of several blocks. Most of the blocks...

FIR Filter Design Based on FPGA

 The paper introduces structure characteristics and the basic principles of the finite impulse response (FIR) digital filter, and gives an efficient FIR filter design based on FPGA. Use MATLAB FDATool to determine filter coefficients, and designed a 16-order constant coefficient FIR filter by VHDL language, take use of QuartuslI to simulate filters,...

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

 In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commerc...

An Efficient VLSI Architecture for Convolution Based DWT Using MAC

 The modern real time applications related to image processing and etc., demand high performance discrete wavelet transform (DWT). This paper proposes the floating point multiply accumulate circuit (MAC) based 1D/2D-DWT, where the MAC is used to find the outputs of high/low pass FIR filters. The proposed technique is implemented with 45 nm CMOS tech...

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS

 This paper presents a low-power 12-bit 100-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC). Several techniques are developed to enhance the ADC performance. The nonbinary capacitor array with small digital-to-analog converter (DAC) capacitors (total 394 fF) allows for reducing DAC settling time and power co...

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

 In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-sw...

Low Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphism Encryption

 Large integer multiplication has been widely used in fully homomorphic encryption (FHE). Implementing feasible large integer multiplication hardware is thus critical for accelerating the FHE evaluation process. In this paper, a novel and efficient operand reduction scheme is proposed to reduce the area requirement of radix-r butterfly units. We als...

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications

 Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (E...

Combating Data Leakage Trojans in Commercial and ASIC Applications with Time Division Multiplexing and Random Encoding

 Globalization of microchip fabrication opens the possibility for an attacker to insert hardware Trojans into a chip during the manufacturing process. While most defensive methods focus on detection or prevention, a recent method, called Randomized Encoding of Combinational Logic for Resistance to Data Leakage (RECORD), uses data randomization to pr...

Approximate Sum of Products Designs Based on Distributed Arithmetic

 Approximate circuits provide high performance and require low power. Sum-of-products (SOP) units are key elements in many digital signal processing applications. In this brief, three approximate SOP (ASOP) models which are based on the distributed arithmetic are proposed. They are designed for different levels of accuracy. First model of ASOP achie...

A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme

 This paper presents a 12-bit 40-MS/s successive approximation register analog-to-digital converter (ADC) for ultrasound imaging systems. By incorporating a fast binary window digital-to-analog converter (DAC) switching technique, the problematic most significant bit transition glitch was removed to improve linearity without increasing the input cap...

World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s

 This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the ...

TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier

 A scalable approximate multiplier, called truncation- and rounding-based scalable approximate multiplier (TOSAM) is presented, which reduces the number of partial products by truncating each of the input operands based on their leading one-bit position. In the proposed design, multiplication is performed by shift, add, and small fixed-width multipl...

Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation

 Approximate addition is a technique to trade off energy consumption and output quality in error-tolerant applications. In prior art, bit truncation has been explored as a lever to dynamically trade off energy and quality. In this brief, an innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to stateo...

Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA

 In this paper, a new pseudorandom number generator (PRNG) based on the logistic map has been proposed. To prevent the system to fall into short period orbits as well as increasing the randomness of the generated sequences, the proposed algorithm dynamically changes the parameters of the chaotic system. This PRNG has been implemented in a Virtex 7 f...

Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate

 This paper describes a bandwidth (BW)- and slew rate (SR)-enhanced class AB voltage follower (VF). A thorough small signal analysis of the proposed and a state-of-the-art AB-enhanced VF is presented to compare their performance. The proposed circuit has 50-MHz BW, 19.5-V/µs SR, and a BW figure of merit of 41.6 (MHz × pF/µW) for CL = 50 pF. It provi...

A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift

 We present a novel generalization of quadrature oscillators (QVCO) which we call “arbitrary phase oscillator” or APO for short. In contrast to a QVCO which generates only quadrature phases, the APO is capable of continuously generating any desired phase at its output. The proposed structure employs a novel coupling mechanism to generate arbitrary p...

New Majority Gate Based Parallel BCD Adder Designs for Quantum-dot Cellular Automata

 In this paper, we first theoretically re-defined output decimal carry in terms of majority gates and proposed a carry lookahead structure for calculating all the intermediate output carries. We have used this method for designing the multi-digit decimal adders. Theoretically, our best n-digit decimal adder design reduces the delay and area-delay pr...

Low-Complexity 2-D Digital FIR Filters Using Polyphase Decomposition and Farrow Structure

 This paper proposes a novel realization technique for quadrantally symmetric 2-D finite impulse response filters with a guaranteed reduction in the hardware complexity. Here, the concept of Farrow structure-based interpolation filter design using the polyphase decomposition of the 1-D filter transfer function is effectively utilized in the 2-D doma...

Low Power Near Threshold 10T SRAM Bit Cells with Enhanced Data Independent Read Port Leakage for Array Augmentation in 32nm CMOS

 The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swi...

A Nanopower Biopotential Lowpass Filter Using Sub threshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

 A nanopower CMOS 4 th -order lowpass filter suitable for biomedical applications is presented. The filter is formed by cascading two types of subthreshold current-reuse biquadratic cell. Each proposed cell is capable of neutralizing the bulk effect that induces the passband attenuation. The nearly 0 dB passband gain can thus be maintained while the...

A Low Complexity I/Q Imbalance Calibration Method for Quadrature Modulator

 This brief presents a low-complexity I/Q (in-phase and quadrature components) imbalance calibration method for the transmitter using quadrature modulation. Impairments in analog quadrature modulator have a deleterious effect on the signal fidelity. Among the critical impairments, I/Q imbalance (gain and phase mismatches) deteriorates the residual s...

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage

 This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue i...

Radiation Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Applications

 In this paper, a novel radiation-hardened 14-transistor SRAM bitcell with speed and power optimized [radiation-hardened with speed and power optimized (RSP)-14T] for space application is proposed. By circuit- and layout-level optimization design in a 65-nm CMOS technology, the 3-D TCAD mixed-mode simulation results show that the novel structure is ...

Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery

 Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short...

Line Coding Technique for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

 This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manches...

Efficient Design for Fixed Width Adder-Tree

 Conventionally, fixed-width adder-tree (AT) design is obtained from the full-width AT design by employing direct or post-truncation. In direct-truncation, one lower order bit of each adder output of full-width AT is post-truncated, and in case of post-truncation, {p} lower order-bits of final-stage adder output are truncated, where p = dlog2 Ne and...

CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

 A CMOS fully integrated all-pass filter with an extremely low pole frequency of 2 Hz is introduced in this paper. It has 0.08-dB passband ripple and 0.029-mm2Si area. It has 0.38-mW power consumption in strong inversion with ±0.6-V power supplies. In subthreshold, it has 0.64-µW quiescent power and operates with ±200-mV dc supplies. Miller multipli...

A Novel Design of Flip-Flop Circuits using Quantum Dot Cellular Automata(QCA)

 As the device dimension is shrinking day by day the conventional transistor based CMOS technology encounters serious hindrances due to the physical barriers of the technology such as ultra-thin gate oxides, short channel effects, leakage currents & excessive power dissipation at nano scale regimes. Quantum Dot Cellular Automata is an alternate chal...

Multiloop control for Fast Transient DC-DC Converter

 A novel ac coupled feedback (ACCF) is proposed to alternatively realize fast transient response while inherently controlling the start-up in-rush current of a dc–dc switching converter. The proposed ACCF is modified from a conventional capacitor multiplier and connected between the outputs of the converter and the transconductance. With this supple...

Feed forward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator

 Multiply–accumulate (MAC) computations account for a large part of machine learning accelerator operations. The pipelined structure is usually adopted to improve the performance by reducing the length of critical paths. An increase in the number of flip-flops due to pipelining, however, generally results in significant area and power increase. A la...

Design of Reconfigurable Digital IF Filter with Low Complexity

 Due to limited frequency resources, new services are being applied to the existing frequencies, and service providers are allocating some of the existing frequencies for newly enhanced mobile communications. Because of this frequency environment, repeater and base station systems for mobile communications are becoming more complicated, and frequenc...

An Analog LO Harmonic Suppression Technique for SDR Receivers

 A low-complexity analog technique to suppress the local oscillator (LO) harmonics in software-defined radios is presented. Accurate mathematical analyses show that an effective attenuation of the LO harmonics is achieved by modulating the transconductance of the low-noise transconductance amplifier (LNTA) with a raised-cosine signal. This modulatio...

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories

 In this paper, a double-error-correcting and tripleerror-detecting (DEC-TED) Bose–Chaudhuri–Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects th...