Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
Abstract : A poly-phase based interpolation filter computation involves an input-matrix and coefficient-matrix of size (P×M) each, where P is the up-sampling factor and M=N/P, N is the filter length. The input-matrix and the coefficient-matrix resizes when P changes. An analysis of interpolation filter computation for different up-sampling factors is made in this paper to identify redundant computations and removed those by reusing partial results. Reuse of partial results eliminates the necessity of matrix resizing in interpolation filter computation. A novel block-formulation is presented to share the partial results for parallel computation of filter outputs of different up-sampling factors. Using the proposed block formulation, a parallel multiplier-based reconfigurable architecture is derived for interpolation filter. The most remarkable aspect of the proposed architecture is that, it does not require reconfiguration to compute filter outputs of an interpolation filter for different up-sampling factor. The proposed structure has regular data-flow and it has no overhead complexity for its reconfigurable feature unlike the existing structures. Besides, the proposed structure has significantly less register complexity than the existing structure and its register complexity is independent of the block-size. Moreover, the proposed structure can support higher input-sampling frequency than the existing structure. ASIC synthesis result shows that the proposed structure for block-size 4, filter length 32, and up-sampling factor 8, involves 13.6 times more area and offers 245 times higher maximum input-sampling frequency compared with the existing multiplier-less structure. It involves 18.6 times less area-delay-product (ADP) and 9.5 times less energy per output (EPO) than the existing multiplier-less structure.
? The proposed structures involve times less storage per output (SPO), and nearly times less energy consumption per output (EPO) compared with the existing structures, where is the input block-size.
? They involve times more arithmetic resources than the best of the corresponding existing structures, and produce times more throughput with less memory band-width (MBW) than others.
? It involves less LUT access per output (LAPO) than the existing structure for block-size higher than 4.
? This architecture provides an efficient area-time power implementation which involves significantly less latency and less area-delay complexity when compared with existing structures for FIR Filter.
? This problem is partially solved by assuming a constant filter length (equal to the length of the largest size filter) for the reconfigurable interpolation filter, where smaller size filters are realized using the same structure by zero padding.
? The folded interpolation filter structure has one major problem.
? One way to address this issue is to swap the configuration bits stored in the memory in and out of the hardware as they are needed during application execution.
? Although it significantly reduces the configuration time,the performance of Partial Reconfiguration (PR) is heavily impacted by design decisions (partitioning and floorplanning) and the long reconfiguration latency (in milliseconds).
• In this paper, a hybrid Farrow algorithm that combines a modulated Farrow filter with a frequency response interpolated coefficient decimated masking filter is proposed for the design of a novel filter with low computational complexity.
• A transposed modified Farrow structure was proposed for reducing complexity in a Farrow filter by transposing the modified filter and thereby reducing the number of operators.
• The coefficient decimation method (CDM) was proposed to achieve low complexity by using one prototype filter or modal filter.
• A modified form of CDM known as the modified coefficient decimation method (MCDM) was proposed to offer a solution to the variable digital filter.
? Interpolation filter has a different coefficient-vector for different up-sampling factors of a base-band signal.
? A multi-standard SDR system involve interpolators with different filter coefficients, filter-lengths and up-sampling factors to meet the stringent frequency specifications of different communication standards.
? Therefore, a multi-rate interpolation filter structure is more hardware efficient than the single rate interpolation filter structure.
? A novel block-formulation is presented for efficient realization of reconfigurable interpolation filter.
? A parallel reconfigurable architecture is presented for areadelay and power efficient realization of interpolation filters.
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