A Compact 0.3V Class AB Bulk Driven OTA

 In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, wh...

Compact 0.3V AB Bulk Driven OTA ultralow-voltage (ULV) CMOS process MOS transistors

Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

 This paper presents a fully pipelined color demosaicking design. To improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demo...

Quaternary Logic Lookup Table in Standard CMOS

 Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this ...

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

 This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed cl...

A 65-nm CMOS Constant Current Source With Reduced PVT Variation

 This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated volta...

Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders

 This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high powerdelay ...

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

 This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial point...

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

 A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition...

EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control

 A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored contents rather than addresses. The additional don’t care (X) state makes the TCAM suitable for many network applications but the large amount of cell requirement for storage consumes high power and takes a large design area. This p...

A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC

 Inverter-based implementation of operational transconductance amplifiers is an attractive approach for low voltage realization of analog subsystems. However, the high sensitivity of inverter like amplifiers’ performance to process and temperature variations limit the achievable performance of the whole system across process and temperature corners....

A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications

 Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large a...

Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

 Ring oscillators (ROs) are popular due to their small area, modest power, wide tuning range, and ease of scaling with process technology. However, their use in many applications is limited due to poor phase noise and jitter performance. Thermal noise and flicker noise contribute jitter that decreases inversely with oscillation frequency. This paper...

A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

  This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDL...

A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

 This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS pr...

A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

 A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from ...

Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology

 One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of improvement has been done in this area to refine the architecture and performance of full adder circuit design. In this paper two designs of novel ...

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS

 This paper presents a low-power 12-bit 100-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC). Several techniques are developed to enhance the ADC performance. The nonbinary capacitor array with small digital-to-analog converter (DAC) capacitors (total 394 fF) allows for reducing DAC settling time and power co...

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

 In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-sw...

A Nanopower Biopotential Lowpass Filter Using Sub threshold Current-Reuse Biquads With Bulk Effect Self-Neutralization

 A nanopower CMOS 4 th -order lowpass filter suitable for biomedical applications is presented. The filter is formed by cascading two types of subthreshold current-reuse biquadratic cell. Each proposed cell is capable of neutralizing the bulk effect that induces the passband attenuation. The nearly 0 dB passband gain can thus be maintained while the...

Line Coding Technique for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping

 This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manches...

Multiloop control for Fast Transient DC-DC Converter

 A novel ac coupled feedback (ACCF) is proposed to alternatively realize fast transient response while inherently controlling the start-up in-rush current of a dc–dc switching converter. The proposed ACCF is modified from a conventional capacitor multiplier and connected between the outputs of the converter and the transconductance. With this supple...

Design of Reconfigurable Digital IF Filter with Low Complexity

 Due to limited frequency resources, new services are being applied to the existing frequencies, and service providers are allocating some of the existing frequencies for newly enhanced mobile communications. Because of this frequency environment, repeater and base station systems for mobile communications are becoming more complicated, and frequenc...

A 2.4 GHz Power Receiver Embedded With a Low-Power Transmitter and PCE of 53.8%, for Wireless Charging of IoT Wearable Devices

 This article presents a 2.4 GHz and high-efficiency wireless power receiver (Rx) integrated with a low-power transmitter (Tx) for wireless charging of the Internet-of-Things (IoT) or wearable devices. A single pole double throw (SPDT) circuit isolates the operation of the Rx from Tx, thereby offering the capability of sharing antenna between them. ...

An Inductorless Wideband Gm-boosted Balun LNA with nMOS-pMOS Configuration and Capacitively Coupled Loads for sub-GHz IoT Applications

 This brief presents an inductorless gm-boosted wideband balun low noise amplifier (LNA) for low power sub-GHz IoT applications. The proposed common source (CS) -common gate (CG) based gm-boosted balun LNA uses nMOS-pMOS configuration for doubling the transconductance and gain efficiency. Loads of CS and CG stages are capacitively coupled to remove ...

A 197.1-µW Wireless Sensor SoC With an Energy-Efficient Analog Front-End and a Harmonic Injection-Locked OOK TX

 This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation a...

A 6-Bit 1.5-GSs SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications

 High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. Th...