Quaternary Logic Lookup Table in Standard CMOS
ABSTARCT :
Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 µW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.
EXISTING SYSTEM :
? To achieve this, existing synthesis tools will be analyzed to determine the most suited for this application. The chosen one will be examined to see what features and functionalities it provides and which are missing.
? It will be extended with new functionalities with the purpose of overcoming existing gaps and perform the desired goal.
? The existing network representation stored in the MVSIS framework has the same functionality, but does not have an accurate representation of the internal nodes.
? This was the main deciding factor on which algorithm to use in this work since no previous tool existed and a base platform with the broadest compatibility is very important.
DISADVANTAGE :
? An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL), hence, more information can be carried in each wire, reducing the routing network.
? However, a solution for this problem is to use an nMOS in series with N1, avoiding the drain-source voltage to be higher than VDD, in each transistor.
? These drawbacks have prevented MVL from being competitive when compared with binary logic.
? This decoder is based on voltage-mode self-referenced comparators that allows the use of a standard CMOS technology and overcomes previous design drawbacks.
PROPOSED SYSTEM :
• The propose QLUT is made out of two block: 16-1 multiplier utilizing a variety of switches that sets up a low-resistance way between one setup input and the output as per the input esteems.
• In the proposed method, here we use the direct technique to do the work in a single clock cycle.
• The proposed design of half adder & full adder using quaternary logic has better function as compared to binary logic.
• The proposed gates allow designing any MVL digital circuit taking advantage of the knowledge coming from the binary circuits.
• Several MVL devices have been proposed and some are in use, such as memories, combinational circuits such as adders and multipliers, as well as programmable devices.
ADVANTAGE :
? We have to consider the pad, bonding wire, PCB wire and probe, which will degrade the performance of the real signal applied to the circuit.
? The exposed limitations encourage the exploration of circuit and system-level techniques to achieve higher energy efficiency.
? The proposed MVL LUT can replace or complement conventional binary logic, since the designed circuit is simple, efficient and we can combine both; i.e., they use the same implementation/fabrication technology.
? However, in spite of these advantages, it is known that the use of MVL comes at the price of having relatively lower noise margin than the binary, therefore its use is commonly not trusted.
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