Low Power High Speed 1-bit Full Adder Circuit design at 45nm CMOS Technology
Abstract : One bit full adder cell is one of the most frequently used digital circuit component in arithmetic logic unit (ALU) and it is the essential functional unit of all computational circuit. Till now lots of improvement has been done in this area to refine the architecture and performance of full adder circuit design. In this paper two designs of novel 1-bit full adder cell at 45nm CMOS technology is implemented by using ten transistors (10-T) along with the three existing 1-bit full adder cell. Later the complete comparison and verification is performed with the different existing and proposed adder cells on different supply voltages at 100MHz operating frequency. From the simulation results by performing the comparison among proposed adder cells and existing adder cells it is found that the proposed adder cells are better than the existing adder cells in terms of power consumption, delay and power delay product (PDP). From the simulation result it is observed that the first proposed adder circuit using XOR module has achieved maximum saving of power 91.65%, saving of delay 59.37% and saving of overall PDP of 91.64% when compared to existing Static Energy Recovery Full (SERF) full adder and Gate Diffusion Input (GDI) full adder circuit respectively. When second proposed adder circuit using XOR module is compared with existing SERF and GDI adder circuit maximum saving of power 93.04%, saving of delay 76.76% and saving of overall PDP of 96.01% is achieved. All above statistical analysis is given by performing the comparison between existing and proposed adder circuits which have same number of transistors count (10-T) in designing at supply voltage 1 volt.
? This problem exists in the circuits that use the transmission function theory in their implementation without buffering output.
? We try to remove the problems existing in the investigated circuits. Afterward, with these new XOR/XNOR and XOR–XNOR circuits, we have a tendency to propose six new FA structures.
? The planned circuit for concurrent XOR–XNOR has higher potency altogether 3 calculated parameters (delay, power dissipation, and PDP) once it's compared with different XOR–XNOR gates.
? The proposed XOR–XNOR circuit is saving almost 16.2%–85.8% in PDP, and it is 9%–83.2% faster than the other circuits.
? Due to voltage loss problem and also the major problem of a GDI full adder cell is that it requires twin-well CMOS or Silicon On Insulator (SOI) process to construct it, so it will be more expensive to implement a GDI chip.
? If GDI uses only standard p-well CMOS process to implement it, the new problem arises that is decrease in driving capability which makes this process more expensive and also not easy to realize.
? The problem with SERF and GDI one bit full adder is output voltage swing which is also present in proposed 1-bit adder cell but it has better performance (less delay), lesser power consumption and efficiently less power delay product.
• In this paper the proposed technique for high speed and low power for designing 16T full adder is MTCMOS in 45nm regime.
• With the increased no. of transistor many leakage current comes under picture like subthreshold conduction current, gate direct tunnelling current, punch-through current.
• Many techniques have been proposed to reduce these leakages. The most effective technique is MTCMOS.
• MTCMOS technique is proposed to satisfy the lower threshold voltage requirement as well as to increase the speed of the circuit.
• The power dissipation and delay is the main issue in nm technology. In this paper MTCMOS technique is proposed to reduce these two parameters.
? All digital communication devices have multiple numbers of 1-bit full adder cells integrated within it to perform one or many bits addition operation, this is the reason adder cell plays an important role in determining the performance of the whole system.
? To reduce the area of chip, the complexity in the circuits has increased significantly, because of that the power dissipation and performance of the adder circuit are being affected.
? Power delay product (PDP) is a parameter which is used in this paper for comparison between various adder circuits to estimate the optimized results either at a single operating frequency or at different operating frequency regions .
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