A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS
Abstract : This paper presents a low-power 12-bit 100-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC). Several techniques are developed to enhance the ADC performance. The nonbinary capacitor array with small digital-to-analog converter (DAC) capacitors (total 394 fF) allows for reducing DAC settling time and power consumption while maintaining extremely high hardware utilization. The proposed nonlinear capacitance correction method solves the nonlinear capacitance problems of the comparator when the small unit capacitor is used. The latch output glitch removal method ensures the speed and accuracy of the comparator at the low supply voltage. Furthermore, the proposed high-speed SAR logic and timing sequence improved SAR logic’s operating speed by 75% compared with traditional SAR logic. The prototype was fabricated using a 40-nm CMOS technology. At a 0.9-V supply and 100-MS/s sampling rate, the ADC achieves a signal-to-noise distortion ratio of 67.3 dB and consumes 2.6 mW, resulting in a figure of merit of 14.6 fJ/conversion-step. The ADC core occupies an active area of only 50 × 280 µm2.
? The power and area efficiency mainly benefit from the advanced process, low power supply, parallel split capacitor array and single-side-fixed technique.
? For every type of SAR ADCs, linearity of sampling switch is the bottleneck for system linearity, the parasitic diodes of source/drain to substrate exist in the sampling switch.
? Moreover, a single-side-fixed technique is utilized to reduce the number of capacitors.
? The conventional MCS switching procedure has the unswitched dummy capacitor in the last conversion step, while the proposed one takes full advantage of the capacitor.
? It is not a serious potential problem in synchronous logic, but the timing logic may collapse in asynchronous SAR ADC.
? The small unit capacitor provides the advantages as described earlier, it leads to the charge injection and leakage problems of the top plate.
? This may have a direct impact on the comparison result and the subsequent conversions.
? In this paper, a power- and area-efficient SAR ADC with high linearity in a 28 nm CMOS process is presented, which requires no calibration.
• To demonstrate the proposed technique, a design of 12- bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB.
• The proposed ADC core occupies an active area of 0.02 mm2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.
• A small Cc is used to bias the PW instead of additional switches in, low on-impedance is achieved with small parasitic capacitance in the proposed structure.
• To demonstrate the proposed linearity-enhanced switch technique, we design the four sampling switches with the same size in 40 nm CMOS technology.
? There are many techniques that have been reported for implementing high-performance SAR ADCs.
? However, with small DAC capacitors, a variety of factors will limit the ADC performance, such as capacitor mismatches, the top plate parasitic capacitors, the comparator input nonlinear parasitic capacitors, and the leakage and clock feedthrough of the top plate switches.
? The performance of the ADC is mainly limited by this deterministic capacitor mismatch.
? High-speed and high-resolution analog-to-digital converter (ADC) can be widely used in smart antenna systems, mobile communications, and other fields and at the same time, high energy efficiency is still required in these ADCs.
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