A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC
Abstract : Inverter-based implementation of operational transconductance amplifiers is an attractive approach for low voltage realization of analog subsystems. However, the high sensitivity of inverter like amplifiers’ performance to process and temperature variations limit the achievable performance of the whole system across process and temperature corners. In this paper, a tuning technique is proposed to maintain the inverterbased amplifier performance across the process and temperature corners without requiring additional voltage headroom than that required by the inverter circuit. The introduced technique is used to implement a third-order continuous-time sigma–delta (–) analog-to-digital converter (ADC). The main building block of the implemented ADC is an inverter-based amplifier. This makes the resulting – ADC easier to scale to different technology nodes. A 74-dB signal-to-noise and distortion ratio is achieved, for a signal bandwidth of 64 kHz at a sampling frequency of 6.4 MHz, while consuming 400 µA from a 0.8 V supply in 65-nm CMOS technology.
? Existing strategies to compensate PVT variations increase the OTAs design complexity, and the development of new compensation strategies is an open research field.
? Existing techniques for the design of inverter-based amplifiers are analyzed and used as a starting point to develop novel amplifier topologies.
? One must determine the NTF of the modulator and map the NTF to one of the existing SDM architectures.
? The CT-SDMs intrinsic anti-alias filter ceases to exist because the input signal is applied directly to the input of the quantizer and is not filtered by the low-pass filter of the modulator.
? A main disadvantage of operating the inverter as an amplifier is the high variation of the inverter dc gain and gain bandwidth (GBW), with temperature and process corners.
? A reduction in the dc gain of an amplifier directly impacts the performance of continuous time (CT) sigma–delta (–) analog-to-digital converter (ADC) by raising the noise floor, which consequently degrades the signal-to-noise ratio.
? However, high-order modulators are conditionally stable and instability problems can arise in modulators with no proper coefficient scaling.
? The loop filter integrators should present reduced output swing to minimize linearity issues.
• The proposed architecture has been validated by designing OTAs in 180 nm standard CMOS process for operation on 1.8 V supply.
• A 1-bit third order DTDSM has been designed using the second OTA to prove that the proposed design fits well for SC applications.
• This research proposes an architecture for inverter-based OTA to realize high DC gain while keeping the quiescent current to a low value.
• The proposed IGB-OTA can easily achieve a DC gain in excess of 90 dB with careful sizing and biasing of transistors.
• The performance of the proposed OTA is also compared with OTA’s operating on lower supply voltage and it is presented.
? The proposed circuit is used to build a CT – ADC, and the worst case performance across the process and temperature variations is reported.
? This input level, the performance of the modulator degrades, as the second and third harmonics contribution becomes relatively high, and effectively raises the modulator overall noise floor.
? The achieved performance is compared with prior art measurements, only to show how this paper may fit within the state of the art.
? The mapped coefficients are selected to maintain a stable operation of the ADC for specific input ranges.
? All loop filters coefficients are scaled to obtain a reasonable signal swing at the integrators outputs and the comparator input.
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