A Compact 0.3V Class AB Bulk Driven OTA
Abstract : In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time.
The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.
In recent years, there has been an increased interest in the design of ultralow-voltage (ULV) and ultralow-power (ULP) analog circuits. This new trend is mainly motivated by the increased demand for power-efficient solutions used in medical implantable or wearable devices, wireless sensor nodes, and other similar applications.
Lower supply voltage allows decreasing the dissipated power of both, analog as well as a digital portion of the above-mentioned systems. One of the most widely used analog building blocks in CMOS circuits is the operational trans conductance amplifier (OTA). A number of ULV OTAs have been proposed in the literature in recent years. It is worth noting that more and more of these circuits can operate even from deep sub0.5-V supply.
low trans conductance
lower voltage gain
larger input noise and offset
In this paper presents a operational trans-conductance amplifier (OTA) to provide a novelty for an ultralow voltage (ULV), ultralow power (ULP). In the Miller Zero compensation technique of multipath method will required low voltage driven with a combination of non-tailed differential bulk driven.
Thus, a straightforward class of AB low power efficient ULV structure have been acquire, which can work on the supply voltages below the threshold of the MOS transistors used. While simultaneously providing the common more range of the input rail to rail. The existing method of OTA based architecture was developed at 180nm CMOS technology using 0.3V at 3.5 KHz frequency.
In the proposed method of OTA architecture was developed at 22nm CMOS technology using 0.2V at 100 KHz frequency, finally this work as developed in Tanner EDA tool, and proved the comparison of delay and power consumptions. The schematic of the proposed amplifier is shown in Fig. 1. The circuit can be considered as a two-stage Miller OTA with an additional feed forward path (M5–M7) used to compensate for the right-half-plane (RHP) zero introduced by the compensation capacitance CC.
The input stage (M1–M4) is based on the idea of a non tailed BD differential pair with gain boosting. The circuit can operate with very low supply voltage (VDDmin = 2 VDSsat) while offering good CMRR, power supply rejection ratio (PSRR), and rail-to-rail ICMR at the same time.
In addition, the circuit operates in class AB, which increases its SR performance. It is worth noting that its noise properties and the input-referred offset are not worse than achieved for a conventional BD differential pair.
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