Low-Power and Area-Efficient Shift Register Using Pulsed Latches
ABSTARCT :
This paper proposes a low-power and area-efficient shift register using pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a small number of the pulsed clock signals by grouping the latches to several sub shifter registers and using additional temporary storage latches. A 256-bit shift register using pulsed latches was fabricated using a 0.18 µm CMOS process with VDD=1.8V. The core area is 6600 µm 2 . The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops.
EXISTING SYSTEM :
? The Existing method comprises of the design of the shift register by using pulsed latches.
? Moreover the Architecture of the shift register consists of pulsed clock generator which is used for generating clock pulses to the latches.
? The operation of the existing shift register is same as performed by the proposed shift register.
? The proposed system uses the less number of latches compared to the existing system. The same shifting operation has been done in the Register Reusing concept.
? In VLSI modular technology it majorly deals with reducing interconnecting fabricating microchip Area.
DISADVANTAGE :
? The pulsed latch cannot be used in a shift register due to the timing problem between pulsed latches.
? The shift register solves the timing problem using multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal.
? Each latch has a constant input during its clock pulse and no timing problem occurs between latches. However, this solution also requires many delay circuits.
? The pulse skew differences between the different sub shift registers do not cause any timing problem, because two latches connecting two sub shift registers use the first and last pulsed clocks which have a long clock pulse interval.
PROPOSED SYSTEM :
• This paper proposes a low-power and territory proficient move enlist utilizing computerized beat locks.
• The proposed move enroll utilizes hooks rather than flipflops to decrease the region and power utilization.
• This paper proposes a low power and area efficient shift register by register reusing.
• This paper proposes a N-bit shift Register by using register reusing concept. The pulsed latch has been used to reduce the time delay in the circuits.
• Due to Register Reusing the area time and delay has been reduced greatly in proposed shift register.
ADVANTAGE :
? This paper proposes a low-power and area-efficient shift register using pulsed latches.
? Two 256-bit area-efficient shift registers using the SSASPL and PPCFF were implemented to show the effectiveness of the proposed shift register.
? A shift register is the basic building block in a VLSI circuit. Shift registers are commonly used in many applications, such as digital filters, communication receivers, and image processing Ics.
? Each latch uses a pulsed clock signal which is delayed from the pulsed clock signal used in its next latch.
? A small number of the pulsed clock signals is used by grouping the latches to several sub shifter registers and using additional temporary storage latches.
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