ADVANTAGE :
? This paper proposes a low-power and area-efficient shift register using pulsed latches.
? Two 256-bit area-efficient shift registers using the SSASPL and PPCFF were implemented to show the effectiveness of the proposed shift register.
? A shift register is the basic building block in a VLSI circuit. Shift registers are commonly used in many applications, such as digital filters, communication receivers, and image processing Ics.
? Each latch uses a pulsed clock signal which is delayed from the pulsed clock signal used in its next latch.
? A small number of the pulsed clock signals is used by grouping the latches to several sub shifter registers and using additional temporary storage latches.