A Robust Energy Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
ABSTARCT :
This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS process scaling, enables the receiver to achieve low power and area consumption. The ADCDR can enter into open loop after lock-in to save power and avoid clock dithering phenomenon. Moreover, to compensate the open loop, a phase tracking procedure is proposed to enable the ADCDR to track the phase drift due to the voltage and temperature variations. Furthermore, the all-digital delay-locked loop circuit integrated in the ADCDR can generate accurate multiphase clocks with the proposed calibrated locking algorithm in the presence of process variations. The precise multiphase clocks are essential for the half-rate sampling and Alexander-type phase detecting. Measurement results show that the receiver can operate at a data rate of 6.4 Gbits/s with a bit error rate <10-12, consuming 7.5-mW per lane (1.2 pJ/bit) under a 0.85 V power supply. With ADCDR’s phase tracking, the receiver performs better in jitter tolerance and achieves a 500-kHz bandwidth, which is high enough to track the phase drift. The receiver core occupies an area of 0.02 mm2 per lane.
EXISTING SYSTEM :
? Most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous amount of dynamic power to charge/discharge the large global clock capacitance.
? All of the CDN efforts to improve signal integrity and power are based on traditional voltage mode (VM) signaling.
? In addition to low power, this scheme showed significant noise robustness compared with the existing VM clocking schemes.
? It is worth mentioning that the proposed methodology is in stark contrast to the existing impedance balancing VM schemes where clustering and load balancing was achieved using wire and/or buffer sizing.
DISADVANTAGE :
? The glitching problem clarified in exists in this NAND-based delay line, which will inject error bits into the recovered data during tracking.
? The idea presented in can address this issue, but at the expense of timing and area cost.
? This paper presents a new all-digital DLL-based CDR using NAND-based delay lines, which can address the above issues.
? The digital design techniques for DLLs/CDRs are described, and the drawbacks of some previous works are discussed as well.
PROPOSED SYSTEM :
• The proposed CDR utilizes a multi-phase multiplying delay-locked loop (MDLL) to generate the eight-phase reference clocks, which achieves multi-phase frequency multiplication with a small area and less power consumption.
• The proposed digital CDR uses a new initial phase tracker that uses a preamble to reduce the lock time.
• The proposed SerDes receiver core consists of a shared multi-phase MDLL, an all-digital PI-based quarter-rate CDR, and a CTLE.
• The proposed CDR adopts a quarter-rate architecture to sufficiently widen the timing margin of the input sampler and to simplify the clock distribution network with much a lower sampling clock frequency.
ADVANTAGE :
? To meet the demand for the massive data throughput in high-performance computing systems, the bandwidth of these links has been increasing aggressively.
? Therefore, improving power efficiency has become the major concern of the SerDes design as well as the jitter performance.
? The lower supply voltage improves power consumption, while the lower latency improves a digital block’s skew and jitter performance.
? In this paper, a simpler and effective calibration method is proposed to eliminate process mismatch with negligible penalties of the area, power, and performance.
? Phase-locked loop (PLL) and delay-locked loop (DLL) can be used to generate the required clocks.
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