High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

Abstract : A high-speed, low-power, and highly reliable frequency multiplier is proposed for a delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. In addition, by applying the logical effort to the pulse generator and multiplication-ratio control logic design, the proposed frequency multiplier minimizes the delay difference between positive- and negative-edge generation paths, which causes a deterministic jitter. Finally, a numerical analysis is performed to analyze and compare the performance of the proposed frequency multiplier with that of previous frequency multipliers. The proposed frequency multiplier is fabricated using a 0.13-µm CMOS process technology, and has the multiplication ratios of 1, 2, 4, 8, and 16, and an output range of 100 MHz–3.3 GHz. The frequency multiplier achieves a power consumption to a frequency ratio of 2.9 µW/MHz.
 EXISTING SYSTEM :
 ? Many DVS algorithms have been proposed which is productive method to classify such DVS algorithms by excellent multimedia application which does not exist. ? The structures of the recently published frequency multipliers that perform better than most previous frequency multipliers. ? The frequency multiplier is composed of a D-flip–flop-based pulse generator, multiplication-ratio control logic, and a push–pull-stage based edge combiner. ? The frequency multiplier can generate the multiplied differential clocks with a small area penalty.
 DISADVANTAGE :
 ? A small-sized PU-P is no longer required; this property efficiently solves the slow operation problem of the DCVSL-stage-based edge combiner. ? However, the frequency multiplier in still has some problems in common with the frequency multiplier in, including reliability degradation owing to pulse overlapping. ? The normalized maximum multiplied clock frequencies of the frequency multipliers in are less than those of the frequency multiplier in, and the proposed frequency multiplier because of the structural problems. ? The speed and the reliability issues of previous edge combiners, an HSHR-EC, which consists of a precombining stage, overlap canceller, and push–pull stage, is proposed.
 PROPOSED SYSTEM :
 • This paper proposes high complication and time-varying workload of developing multimedia applications possess a major challenge for (DVS) algorithms. • To improve the lock time, which is an imperative design constraint in the clock generator, a dual-edge-triggered phasedetector-based DLL core is adopted. • Alike to previous frequency multipliers, the projected frequency multiplier are also serene of an edge combiner, multiplication-ratio control logic and pulse generator. • The pulse creator marks pulses by using 32-phase differential clocks, for negative and positive-edge generation.
 ADVANTAGE :
 ? Dynamic voltage and frequency scaling (DVFS) is currently being used in nearly every system-onchip (SoC), because DVFS can efficiently lower the dynamic power consumption of the SoCs while maintaining the performance. ? The performance variation of the proposed clock generator with regard to the multiplication ratio and the DLL reference clock. ? However, because FoM1 only concentrates on the aspect of performance, area and multiplication range, which are the most important design parameters for a clock generator, cannot be compared using FoM1. ? The multiplying DLL and the PLL architecture in show superior performance than the proposed clock generator in FoM1.

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