A 65-nm CMOS Constant Current Source With Reduced PVT Variation
Abstract : This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process–voltage–temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated voltageto-current conversion in a preregulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18 µW with a 1.4 V supply. The measured results indicate that the current reference achieves an average temperature coefficient of 119 ppm/°C over 12 samples in a temperature range from -30 °C to 90 °C without any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. This paper offers a better sensitivity figure of merit with respect to the reported representative counterparts.
? There exists another challenge from the non-ideal CMOS stress effect that causes the performance degradation in the PVT-aware circuits.
? The coexistence of the DC/DC and LDO regulators helps to achieve low-noise power supply whilst maintaining high power efficiency.
? Although a good solution for the threshold voltage reference is reported using the weak inversion transistors and linear resistors other than the bipolar transistors, the T.C. is limited by the nonlinear temperature effect existing in VGS(T).
? The increasing demand on the LDO regulators for the portable devices gives rise to one of the motivations on the design of performance-aware LDO regulators.
? These problems have increased the motivation for the design of a low-power constant current reference with reduced PVT variation in the context of aggressively scaled nanometer technology.
? The VTH mismatch issue between the tracking device pair will degrade the current accuracy.
? This is in contrast with the designs from, which suffer from the offset issues induced by the op-amp. In view of D2D variation, the obtained process sensitivity is 5% because it comes from the combined accuracy of the compensation voltage and the sense resistor.
? Turning to the power consumption issue, it is often regarded as the performance trade off parameter.
• The proposed reference voltage by the BGR circuit can also be minimized to the diode voltage level if the supply voltage is reduced to the same level.
• The proposed design achieves a low chip area, a higher temperature range and reasonable TC and PSRR.
• The proposed circuit with pre-regulator will increase the immunity against the supply variation from dc to high frequencies.
• A low T.C. current reference with PVT insensitivity and wide temperature range in 65-nm CMOS technology is proposed.
• Those designs, that deal with the first-order temperature effect from the on-chip resistors, the proposed circuit takes into account the second-order temperature effect.
? The thermal drift over the temperature range is quite small and within 5 nA, demonstrating that the proposed temperature compensation method permits a low T.C. performance metric.
? This paper achieves the best performance in terms of line sensitivity in comparison with the other works except for, in which it benefits from a high supply voltage architecture.
? In particular, it has a lower power consumption except for, which focus on a very low-power circuit design at the expense of a higher T.C. performance metric.
? This paper can offer good FOM values while providing a good balance in the performance metrics like low power consumption and reduced PVT variation.
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