A Low-Voltage Radiation-Hardened 13T SRAM Bit cell for Ultralow Power Space Applications
Abstract : Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by space applications. The most vulnerable of these circuits are memory arrays that cover large areas of the silicon die and often store critical data. Radiation hardening of embedded memory blocks is commonly achieved by implementing extremely large bitcells or redundant arrays and maintaining a relatively high operating voltage; however, in addition to the resulting area overhead, this often limits the minimum operating voltage of the entire system leading to significant power consumption. In this paper, we propose the first radiation-hardened static random access memory (SRAM) bitcell targeted at low-voltage functionality, while maintaining high soft-error robustness. The proposed 13T employs a novel dual-driven separated-feedback mechanism to tolerate upsets with charge deposits as high as 500 fC at a scaled 500-mV supply voltage. A 32×32 bit memory macro was designed and fabricated in a standard 0.18-µm CMOS process, showing full read and write functionality down to the subthreshold voltage of 300 mV. This is achieved with a cell layout that is only 2× larger than a reference 6T SRAM cell drawn with standard design rules.
? The virtual source CNTFET 14 nm model lags behind the read and write delay and compared with existing models.
? There exists a latency to power ON the cells placed farther from the power supply compared to the closest cell.
? Several existing memory architectures, the most commonly used standard memory type is the 6T memory cell.
? To enhance the reliability of these devices, the critical charge of the device is calculated by striking it with a varying energy level.
? The SOI-based FinFET exhibits higher bipolar amplification, it has better reliability against irradiation.
? Such as silicon-oninsulator and other process techniques, can improve the data reliability but do not entirely solve the SEE problems, and often high volume manufacturing is not feasible.
? This either leaves the cell susceptible to half-select failures or eliminates the option of partial row writes—a real problem if bit-interleaving is desired for minimizing the probability of multiple-bit failures.
? Qcoll depends on the type of the ionizing particle, trajectory, energy value, and impact location.
? In order to test the impact of process variations, 12 dies were measured, all of which were operated successfully over the full range of supply voltages, from 300 mV to 1.8 V.
• An optimal approach to reduce the leakage power of a 13T SRAM cell based on 22nm FinFET technology is proposed.
• The proposed bit-cell is designed to enable robust, low-voltage, ULP operation in space applications and other high-radiation environments.
• The read access transistor in the proposed 13T SRAM bit-cell is (N8) this is controlled by a separate read word line connected to a read bit line, read operation is discharged depending on the voltage stored at Q.
• The proposed radiation hardened 13T Static Random Access Memory (SRAM) targeted at low-voltage functionality maintains high soft-error robustness.
? The most efficient way to achieve ULP operation in integrated circuits is to aggressively reduce the supply voltage (VDD) and operate all components of the chip in the near-threshold or subthreshold region, thereby significantly reducing both static and dynamic power consumption.
? Due to their static power consumption, scaling the supply voltage of the SRAM macros is an efficient method to reduce total chip power.
? One of the most simple and efficient solutions that has been proposed to mitigate SEUs is the TMR solution, which utilizes three identical memory arrays and a voting circuit to decide on the correct readout.
? However, as read margin is often the limiting factor in supply voltage scaling, single-ended readout is often used as an alternative to the standard differential readout.
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