A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
Abstract : A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-µm CMOS technology and occupies an area of 0.011 mm2. It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies.
? The proposed PA-ADDCC uses a sequential search with a high-resolution delay line, which can improve the accuracy of the duty-cycle correction as compared with the existing approaches.
? However, because of the half coarse DDCC and half fine DDCC inside it, PA-ADDCC may induce a delay mismatch problem when there are serious OCVs, particularly in an advanced CMOS process.
? However, the duty-cycle detection is carried out by the fullcycle delay line, and the output clock is compensated by the half-cycle delay line.
? The duty-cycle compensation code from the full-cycle delay line to the HCDL is shifted by one bit.
? The value of K impacts the operating frequency range of the DCC loop on the lower side.
? It can make the correction frequency higher and have a larger correction range. Because this structure is highly symmetrical, it can reduce the impact of PVT to very low.
? The conventional level shifter has a problem that is very vulnerable to process corner variation.
? A fundamental solution to the problem of DCC performance degradation caused by the level shifter is to remove the level shifter from the DCC structure.
• The proposed circuit operation frequency is at 0.8GHz to 4GHz, and it correctes to less than 1% error.
• We propose an analog DCC that can correct the bandwidth from 0.8GHz to 4GHz, the correction range can be 20% to 80%, and the correction to 50% accuracy is 1% or less.
• The proposed DCC utilizes a new full-swing duty cycle adjuster (DCA) that can provide a full-swing output clock of 50% duty-cycle without using a small-swing to full-swing level shifter.
• The proposed full-swing DCA is based on a new pseudo-differential feedback delay element (PFDE) and fundamentally eliminates the problem of increased duty-cycle errors due to the use of a level shifter that is vulnerable to process corner variation.
? While the scaling of CMOS transistors has the enhanced digital performance, it has also led to more pronounced intradie and interdie process variation.
? This calls for a design philosophy in which the circuits have the capability to overcome these variations and ensure performance.
? The presence of even order harmonics causes performance degradation in terms of linearity, efficiency, and additional out-of-band components.
? In implementations where a fine phase separation is generated on-chip, non-50% duty-cycle clocks result in direct performance degradation.
? They have the advantage of faster settling time, they are limited by the speed of the technology.
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