Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
ABSTARCT :
In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, powerdelay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.
EXISTING SYSTEM :
? It is occurred when Both pull up transistor and pull down transistor on simultaneously as a result of direct path exist from vdd to gnd with small interval of time.
? In this paper employed a novel design of full adder cell based on sense energy recovery concept using novel XNOR gates is presented.
? When we compare proposed new XNOR gate provide better outcomes compared to the existing work based on speed, power consumption and power delay product (PDP).
? The execution: power, time delay and power delay product (PDP) of the proposed adder cell has been investigated in correlation with the four existent low-power, fast adders.
DISADVANTAGE :
? Optimizing the W/L ratio of transistors is one approach to decrease the power-delay product (PDP) of the circuit while preventing the problems resulted from reducing the supply voltage.
? The main problem of this circuit is using two high power consumption NOT gates on the critical path of the circuit, because the NOT gates must drive the output capacitance.
? One problem of this XOR–XNOR circuit is to have the feedback (cross-coupled structure) on the outputs, which increases the delay and short-circuit power of this structure.
? The main problem of this circuit is the structure of feedback that imposes extra parasitic capacitance to the XOR and XNOR output nodes.
PROPOSED SYSTEM :
• This proposed full adder successfully operated at low supply voltage with excellent signal integrity and driving capability.
• In this paper, a low-control high speed CMOS full adder is proposed for embedded framework.
• The proposed full adder has better improvement in terms of power consumption and area. short circuit currents also eliminated because there is no direct path from vdd to gnd.
• The proposed adder has been used as the basic building for column compression dada multiplier (CCDM).
• The paper proposed the novel plan of a 3T EX-NOR gate using corresponding CMOS and multiplexer.
ADVANTAGE :
? The efficiency of many digital applications appertains to the performance of the arithmetic circuits, such as adders, multipliers, and dividers.
? The optimization methods, such as choosing the optimal circuit structure for the intended purpose, the appropriate logic style, and transistor sizing, have been utilized for improving the performance of circuits.
? The transistor sizing method, which contains reducing or enlarging the width of transistors, is an effective and powerful tool for optimizing the VLSI circuits and should be used in the design process of high-performance circuits.
? A circuit may have a good performance in the single mode but when placed in a larger structure loses its advantages.
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