A 197.1-µW Wireless Sensor SoC With an Energy-Efficient Analog Front-End and a Harmonic Injection-Locked OOK TX
Abstract : This paper presents an integrated ultra-low-power (ULP) wireless sensor system-on-chip (SoC) that can be used for voltage sensing in both Internet of Things applications and bio-potential monitoring. In order to increase the energy efficiency of the analog front-end (AFE), we propose a noise and power efficient push-pull low noise instrumentation amplifier (LNIA) with a built-in ripple reduction loop based on capacitor reuse. A low-power ISM-band harmonic injection locked on-off-keying transmitter (OOK-TX) is also implemented for energy efficient wireless connectivity. Circuit implementations, design considerations, and detailed analysis are presented to improve the overall energy efficiencies of the SoC including the AFE, TX and, the power management unit. The proposed ULP-SoC is fabricated in 130 nm CMOS technology with a total area of 1.92 mm 2 . The total power consumption of the proposed system-on-chip is 197.1~\mu \text{W} which is one of the lowest among state-of-the-art wireless sensor SoC.
? It is due to the simulated transmission lines model which is not fully simplified. Indeed, a distributed oscillator behavior implies that the resistive losses of any TL have to exist even for a conceptual simulation like here.
? For this reason, the stage number of this kind of oscillator is usually limited at two or three (even if it exists some examples with four or five stages in literature.
? After the amplification stage topology choice, the next step is the transmission line (TL) topology choice. Several line topologies exist: microstrip (MS), coplanar (CPW), slotline, stripline, etc...
? The two most used structures in millimeter-wave integrated circuits are the microstrip line and the coplanar line.
? A small voltage-to-frequency gain is preferred in this design to weaken any interference and noise impact on the RO free-running frequency from the tuning nodes.
? Careful design considerations in both schematic and layout, such as choice of large transistor sizes and common-centroid layout, are followed to ensure that the impact of the offset voltages due to the RRL itself can be mitigated.
? A 1-s value of 0.27 mV across 2000 samples is achieved in this design to sufficiently minimize the impact of the RRL offset.
? The RF output has a power of -20 dBm at 913 MHz. Notice that the reference spurs due to the harmonic IL are high yielding a CSR of 41 dB.
? The proposed power-gated low noise amplifier with current second-reuse technique achieves the lowest power consumption of 8.4µW with 7.9dB noise figure and 20.5dB gain in state-of-the-art designs.
? In this work a power-gated LNA with current second-reuse technique and an injection-locked frequency multiplier (ILFM) by edge combining for carrier generation are proposed to minimize the power.
? The proposed injection-locked transmitter and powergated receiver front-end without inductors were designed and fabricated in 40nm CMOS process.
? The proposed power-gated LNA with the current second-reuse technique achieves the lowest power consumption of 8.4µW with 7.9dB noise figure and 20.5dB gain.
? The most straight-forward method to reduce the power efficiency factor (PEF) is by reducing the supply which is also evident in where a PEF of less than four has been achieved.
? Sub-GHz radios for biomedical/IoT applications have emerged to further reduce the power consumption in the last decade where the performance of the reported works.
? It can be observed that the energy efficiency is limited among the reported work with an active power consumption of less than 200 µW.
? Recent works on LNIA all originate from the inverter-based structure due to its compatibility with low supply operation and high noise efficiency.
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