A 6-Bit 1.5-GSs SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
Abstract : High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex, and robust equalization in the digital domain, as well as easily supporting bandwidth-efficient modulation schemes, such as PAM4 and duobinary. However, the power consumption of these ADC front-ends and subsequent digital signal processing is a major issue. This paper presents a 64-way 6 bit 10 GS/s time-interleaved successive-approximation-based ADC front-end that efficiently incorporates a two-tap embedded FFE and a one-tap embedded DFE, providing the potential for a lower complexity back-end DSP and/or decreased ADC resolution. Fabricated in a 1.1V GP 65nm CMOS process, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33 mm 2 core ADC area. The effectiveness of the embedded FFE and DFE is demonstrated with significant timing margin improvement observed for 10 Gb/s operation over several FR4 channels.
? The fundamental functionality of pseudo high voltage driving analog front end (AFE) is demonstrated. We also discuss the detection algorithm consisting of weak and strong classifiers.
? The measurement result showed the feasibility of replacing an existing proximity sensor with detection rate of 83%.
? However, few existing regulator designs have investigated into supporting a spatially large load with realistic grid parasitics.
? This paper presents a system consisting of nine digital low-drop-out regulators based on event-driven control for better supporting such load. At 0.5V (1V) input, our prototype improves the load regulation FoM by 3.9X (9.1X) and current density by 8.7X (2.8X) over the prior state of the arts.
? One way to circumvent this problem is to use sub-ranging SAR architectures. These designs essentially use a high-speed flash ADC to resolve the first few bits, which are then loaded in the capacitive DAC of a conventional SAR ADC that completes the A/D conversion.
? Another promising approach is to pipeline SAR ADCs, which leads to SAR-assisted pipeline or simply pipelined SAR A/D converters.
? Moreover, since the large noise-limited capacitors of DAC2 are not switched at the internal SAR clock frequency, a relatively long time is available for the residue voltage to settle to the required precision, thereby not limiting the ADC conversion speed.
• The proposed time-approximation filter technique approximates a FIR impulse response in time domain via a modulated LO waveform, leading to an equivalent RF bandpass filtering during the frequency up-conversion process.
• The multi-channel transmitter using this detector achieves less than 0.6º root-mean-square (RMS) phase error in 76- to 81-GHz frequency range. Since the proposed phase detector does not rely on the other TX channels, it's easy to extend the number of channels.
• A fully-integrated sub-THz frequency synthesizer is proposed leveraging an RF sub-sampling PLL (SS-PLL) cascaded with an ILFM-based mm-Wave LO generation chain and a sub-THz mixer for frequency extension.
? This observed boost in performance stems from the inherent digital-like architecture of a SAR ADC, which scales well with process and achieves very good energy efficiency.
? It is evident that recent designs cover a wide performance spectrum (conversion speeds from sub-MS/s to several GS/s) and achieve very good power-efficiency at low to moderate conversion speeds (< 100 MS/s).
? Measurement results show good performance across the entire first Nyquist zone with an SNDR of 47 .3 dB at Nyquist input frequency (225 MHz).
? The use of small capacitors in the CDAC reduces its switching power dissipation as well as settling time and is a key factor in improved SAR ADC performance.
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