Design of Low Power, High Performance 2-4 and 4-16 Mixed-Logic Line Decoders
ABSTARCT :
This paper introduces a mixed-logic design method for line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high powerdelay performance. Both a normal and an inverting decoder are implemented in each case, yielding a total of four new designs. Furthermore, four new 4-16 decoders are designed, by using mixed-logic 2-4 predecoders combined with standard CMOS post-decoder. All proposed decoders have full swinging capability and reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative spice simulations at the 32 nm shows that the proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost all cases.
EXISTING SYSTEM :
? In digital systems, discrete quantities of information are represented by binary codes.
? An n-bit binary code can represent up to 2n distinct elements of coded data.
? A decoderis a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines or fewer, if the n-bit coded information has unused combinations.
? The circuits examined in this work are called n-to-m line decoders, and their purpose is to generate the m = 2n minterms of n input variables.
DISADVANTAGE :
? The low-power topologies presented above have a drawback regarding worst case delay, which comes from the use of complementary A as the propagate signal in the case of D0 and I3.
? This method reduces the total number of the active transistors but it has a drawback of the voltage variation is present at the output of each stage it propagating to the final output stage.
? The problem with the CMOS ICs is their dynamic power dissipation and digital switching noise.
? This problem is solved if we use differential amplifier. Because these amplifiers are not only less sensitive to noise but also enable us to bias amplifier and couple the amplifier stage together without the requirement for bypass and coupling capacitor.
PROPOSED SYSTEM :
• In the proposed design uses the transmission gate logic to realize the 14-transistor low power and low power inverted design, 15-transistor high power and high power inverted decoder designs to achieve the low power, high performance and less die area.
• All proposed decoders have full swinging capability and reduced transistor count compared to their conventional CMOS counterparts.
• The proposed low power , high performance 2-4 and 4-16 line decoder circuits were designed using 65nm CMOS process in Microwind, the size of PMOS is triple that of the NMOS transistor size to achieve the best power and delay performance.
ADVANTAGE :
? They consist of complementary nMOS pulldown and pMOS pullup networks and present good performance as well as resistance to noise and device variation.
? This work develops a mixed-logic design methodology for line decoders, combining gates of different logic to the same circuit, in an effort to obtain improved performance compared to single-style design.
? At a small scale, circuits based on pass transistor logic can realize logic functions with fewer transistors and improved performance compared to static CMOS.
? However, we consider their use in the implementation of AND/OR logic, as demonstrated in, which can be efficiently applied in line decoders.
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