A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM
Abstract : This paper presents a wide-voltage-range, fast-transient all-digital buck converter using a high-resolution digital pulsewidth modulator (DPWM). The converter employs the multithreshold-voltage band-control technique to shorten its transient response. The DPWM uses an all-digital delay-locked loop (ADDLL) to control its cycle. The usage of ADDLL leads to the DPWM possessing a small area while maintaining high cycle resolution. Moreover, the proposed ADDLL-based cyclecontrolled DPWM can achieve synchronization between its input and output. This decreases the loop delay of the proposed converter so that the system is easy to be stabilized. The prototype chips of both the ADDLL-based cycle-controlled DPWM and the all-digital buck converter are fabricated in 0.35-µm CMOS process. Measurement results of the cyclecontrolled DPWM show that the duty cycle of its output is adjustable from 1% to 99% in a 0.78% increment per step when operating at 1 MHz. The measured transition time of the all-digital buck converter is <3.5 µs when the load current changes from 50 to 500 mA, and vice versa.
? All existing one-cycle control converters are designed to have a fixed output.
? However, the transient speed of existing hysteretic converters is still constrained by the inductor.
? To overcome this limitation, an auxiliary current pump is applied to bypass the inductor, compensating the load current change for enhanced transient response.
? Some of them focus on speeding up the controller stage at the expense of increased system complexity.
? Several voltage-triggering current pump sources inject auxiliary current by detecting the output voltage directly, supporting fast auxiliary current injection.
? The offset voltage of the hysteresis comparator has little impact on the stability of the buck converter because the offset voltage can be made very small by proper design and layout of the comparator.
? The delay from the hysteresis comparator has little impact on the stability of the buck converter.
? The advantages and disadvantages of one-cycle control for adaptive-output converter design are addressed.
? However, power efficiency of single-phase DC-DC converters becomes problematic when the peak current reaches several amperes.
? However, there are also some design problems for the DC-DC converters utilizing hysteretic control.
• A dc level shifting technique is proposed to eliminate the use of negative supply and reference voltages in the controller and make the design compatible with standard digital CMOS process.
• An integrated adaptive-output buck converter is proposed in this paper that adopts a dual-loop one-cycle control for fast response and tight voltage regulation.
• All the proposed techniques can be applied to other kinds of converters, such as boost and flyback converters.
• The proposed converter was fabricated in a standard 0.5- m digital CMOS n-well process.
• Design techniques such as dc level shifting, ECL and DLC are proposed to optimize the overall performance of the converter.
? One of the critical components in the power management domain is the dc/dc converter, such as the buck converter, due to its high conversion efficiency.
? The operating frequency of the converter worsens the switching loss dramatically and lowers the converter’s conversion efficiency.
? The efficiency is lowered when the regulated output is set to 2.7 V due to the increase of switching losses in the light load and the increase of conduction losses in the heavy load.
? The proposed buck converter possesses a consistent regulation property and, thus, can be used in a wide variety of applications.
? One-cycle control is a current mode control indeed, but it has more advantages over conventional current-mode counterparts.
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