EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
Abstract : A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored contents rather than addresses. The additional don’t care (X) state makes the TCAM suitable for many network applications but the large amount of cell requirement for storage consumes high power and takes a large design area. This paper presents a novel architecture of TCAM, which prestores 2 bits of data in an up–down manner and provides multiple masking operations through a single control multimasking circuit. The proposed dual bit associative memory with match error and mask control (EMDBAM) consumes low power and selects the valid value on matchline through match error controller. The proposed design has been implemented using a standard 45-nm CMOS technology, and the extracted layout has been simulated using SPECTRE with the supply voltage at 1 V. The proposed EMDBAM can reduce the cell area by 39% compared with a basic TCAM design with a reduction of 9.6% in the energydelay product.
? This is an important feature as it ensures the use of pre-trained models maximizing the integration with existing model architectures.
? The processing element consists of tiny CMOS content addressable memories (CAMs) coupled with a standard floating-point unit (FPU), which is easy to be integrated with modern digital designs, e.g., existing GP-GPUs or custom spatial accelerators.
? There exist solutions with the same accuracy degradation (same Nw), but different associative memory sizes (varying Nin), hence higher or lower energy savings.
? The existing relationship between the prediction accuracy of ConvNets and the design knobs explored in the approximation pipeline.
? This issue has not been resolved in all these architectures. Both CAM and mask storage cells lead to leakage due to the use of cross-coupled inverters.
? The segmented architectures have resolved this issue, but the storage cell count remains the same.
? An 8T SRAM cell has been used for the mask storage to avoid the issue of data storage destruction during the read operation.
? More interesting is the understanding of how the hit rate behavior changes after the apma step to isolate the impact on that stage.
• We proposed a hardware–software co-design flow to implement a fully-CMOS processing element that integrates an SRAM-based CAM into a standard FPU.
• Moreover, with the possibility of controlling the accuracy-latency tradeoff at design-time, ConvNets obtained with the proposed technique cover a larger set of operating points (up to 23% energy savings when the accuracy target gets relaxed from 0.5% to 3%).
• The proposed architecture is inspired to, whose design is more efficient in terms of area and energy compared to a single CAM solution with a double word bit-width (weight
and input concatenation).
? The EMDBAM is adaptable to a supply voltage scaling of 0.6 V without any performance degradation.
? TCAM is a time efficient search device, which clearly outclasses all valid search algorithms in the longest prefix matching and packet classifications.
? A low leakage two-side self-gating (TSSG)-TCAM and basic TCAM for testing the efficacy of our proposed architecture.
? External Bloom filter (BF) has been used to avoid pseudohit and miss events without modifying the CAM architecture.
? A mask storage cell has been placed for each DBAM, and the mask value of it (M or M¯ ) has been used for comparison with the match outputs of both upper and lower CAMs (FL1 and FL2).
|