Energy Efficient Approximate Multiplier Design using Bit Significance Driven Logic Compression
Abstract : Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different bit-widths (4-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay and almost 45% in silicon area can be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.00071 mean relative error. Additionally, we demonstrate the energy-accuracy trade-offs for different degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study image processing application showed up to 68.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).
? Existing work on approximate MAC unit is very scarce comapred to other functional units.
? The proposed design exploits an approximate hybrid redundant adder as the basic building block for both addition and multiplication operations in the MAC unit.
? There exists a considerable amount of efforts to design approximate hardware components.
? The works replace constant multiplications with multiple operations of shift-and-add.
? However, having multiple designs to meet the required quality, mandate a complex controller with a large area overhead.
? These factors have prompted close attention in approximate multiplier design research, since improvements made in the power/speed of a multiplier are expected to substantially impact on overall system power/ performance trade-offs.
? A number of simulations are carried out to examine the impact of error on the proposed approach for different sizes of multiplier.
? However, such error rates can be misleading, as the eventual impact of error is reflected in error distance metrics such as MRED and NMED.
? On a statistical basis, the results of NMED and MRED metrics show how the impact of error is alleviated when the size of the multiplier is increased.
• To our knowledge, the proposed design is the first work that successfully uses highorder approximate compressors in the approximate multiplier design.
• In, different approximate multiplier designs (based on approximate 4:2 compressors) have been proposed to save the power consumption.
• To assess the performance of proposed multipliers (PAWM1 and PAWM2), the DMs such as power, delay, PDP, and area are extracted and compared against the EWM and DAWMs.
• This power advantage can be attributed to the underlying architecture of proposed compressors.
? There is a persistent demand for higher computational performance at low energy cost for emerging applications.
? This can be leveraged as an opportunity for energy-efficient systems design for current and future generations of application-specific systems.
? This allows for building larger energy-efficient multipliers using small approximate ones; however, the hierarchical organization of small approximate blocks will eventually propagate errors which increase with the multiplier size.
? A number of powerand area-efficient multiplier redesign approaches have been proposed by changing the functional behavior.
? We propose a novel energy-efficient approximate multiplier design approach using bit significance-driven logic compression (SDLC).
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