High speed and low power preset-able modified TSPC D flip-flop design and performance comparison with TSPC D flip-flop
Abstract : Positron emission tomography (PET) is a nuclear functional imaging technique that produces a three-dimensional image of functional organs in the body. PET requires high resolution, fast and low power multichannel analog to digital converter (ADC). A typical multichannel ADC for PET scanner architecture consists of several blocks. Most of the blocks can be designed by using fast, low power D flip-flops. A preset-able true single phase clocked (TSPC) D flip-flop shows numerous glitches (noise) at the output due to unnecessary toggling at the intermediate nodes. Preset-able modified TSPC (MTSPC) D flipflop have been proposed as an alternative solution to alleviate this problem. However, the MTSPC D flip-flop requires one extra PMOS to suspend toggling of the intermediate nodes. In this work, we designed a 7-bit preset-able gray code counter by using the proposed D flip-flop. This work involves UMC 180 nm CMOS technology for preset-able 7-bit gray code counter where we achieved 1 GHz maximum operation frequency with most significant bit (MSB) delay 0.96 ns, power consumption 244.2 µW (micro watt) and power delay product (PDP) 0.23 pJ (Pico joule) from 1.8 V power supply.
? Some clock gating circuits were proposed and contrasted and existing ones, to decide the best performed one.
? To defeat the defer augmentation showed in past clock-gated edge-activated flip-flounders, clock-gating a heartbeat activated flip-flop was received and executed by utilizing the best performed check gating plan discovered previously.
? For reliably and a huge bit of the degree of transistors which may be to be melded on a kick the holder gets increased indefinitely?. consequently, the there exists a method implied as the scaling.
? An ideal execution is accomplished when the vitality/postpone affectability of the plan is equivalent for all the structure and innovation factors.
? This problem, the proposed MTSPC DFF architecture reveals that whenever the path to ground is ON, pre-charging node B should be suspended to prevent toggling.
? An Asynchronous Gray counter was proposed to counter these problems. The gray code counter consists of two levels of Flip-Flops in toggle mode operation.
? The proposed technique improves speed, noise and power issue in high frequency gray code counter.
? To cylindrical CNTs, GNRs can be grown through a silicon compatible, transfer-free, and in situ process, thus facing some of the nonalignment and a little bit of transfer-related problems as compared or interfaced by circuits based on CNT.
• In this paper, an investigation of past proposed clock gating plans for flip-flops was done, calling attention to the focal points and downsides displayed for each plan, as far as speed and force scattering.
• A common occurrence, the TSPC D flip flop proposed in has significantly decreased the basic way delay and cleverly expelled the beat generator unit, which brings about an execution of semi static circuit and a particular preferred position as far as both speed and force scattering.
• In, a circuit is proposed which gives better execution in 180nm innovation and depends on the idea of TSPC which is famously known as pre-settable True Single Phase Clock based D flip f.
? As CMOS technology growing towards nanometer scale, the performance of any electronics devices become challenging task because there are several parameter gets affected due to scaled down the devices, researchers have developed various types of logic circuits to increase the performance of a electronics systems.
? The performance of DFFs directly affect the overall performance of the digital circuits.
? In order to obtain higher performances of the circuits, researchers have developed different types of DFFs.
? However there are numerous glitches in the intermediate nodes, due to that the overall performance of the circuit gets degraded.
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