Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs
Abstract : A method is proposed to detect failing cells due to bias temperature instability (BTI) in Static Random Access Memories (SRAMs) en route to failure. If potentially failing cells are detected prior to failure, SRAMs can be operated without failures, since the detection of potentially failing cells can trigger reconfiguration, given available memory redundancy. Using an experimentally verified BTI model, we study the performances of conventional 6T SRAM cells as a function of BTI degradation, in the presence of process variations. An on-chip monitoring scheme is presented that can be embedded within conventional SRAM designs without affecting normal device operation and with minimal overhead.
? In this paper, we look at the implications of NBTI as far as single-event upset (SEU) rate is concerned.
? However, a combination of NBTI and PBTI which exists in most of the real cases has a much bigger effect on the stability and performance of the SRAM cell than the effect due to NBTI only.
? The leakage currents existing in two conditions will be eliminated to a large extent and the write current differential variations show the aging states of the SRAM cells.
? In particular, it has been demonstrated that it degrades SRAM cells in terms of both read and write times and stability.
? This approach cannot detect individual problematic cells, it can create problems with the virtual grounds and is limited by the fact that it cannot monitor the degradation in the memory periphery circuitry.
? Our approach aims to be used in product SRAMs in the field to detect problematic cells, and is not limited to the characterization of SRAMs.
? The problems associated with trying to monitor the strength of the pMOS and nMOS devices in the latch of an SRAM cell.
? To understand the impact of BTI on the reliability of an SRAM array, it is imperative to consider process variations.
• The stress in order to measure the degradation, alternative measurement techniques, such as the on-the-fly methods, which avoid stress interruption, have been proposed.
• In this paper, a compact on-chip degradation technique using runtime leakage current monitoring has been proposed.
• The proposed sensor-based adaptive technique compensates for the variation due to PV and aging using the body-bias-voltage-generator circuit.
• The proposed sensor monitors the change in the leakage current and converts it into voltage which is then used by a measurement circuit to make a decision and perform the mitigation.
? We monitor the degradation of the two pMOS devices and the two nMOS latch devices in each individual cell of an SRAM array without affecting the performances of the cell during normal operation and with little physical overhead.
? The minimum operating voltage is a function of all these performance margins and process variations.
? Some cells will fail to meet the required performance criteria for error free operation, and hence should be replaced by redundant cells using memory reconfiguration.
? The performances of an SRAM cell are dependent on the threshold voltages of all devices, determining the pMOS threshold voltages can be thought of as an increase in the certainty of an event dependent on several random variables by the fixing of two of the random variables.
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