Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
Abstract : In this brief, the implementation of residue number system reverse converters based on well-known regular and modular parallelprefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in nowadays systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix-based adder components that provide better tradeoff between delay and power consumption are herein presented to design reverse converters. A methodology is also described to design reverse converters based on different kinds of prefix adders. This methodology helps the designer to adjust the performance of the reverse converter based on the target application and existing constraints.
? This approach helps the designer to adjust the performance in the proposed modifications of the reverse converter based on the target application and existing curtailments.
? However, several solutions for these problems, which rely heavily on RNS to binary conversion, have been proposed with certain modification to existing systems in the converters.
? In the existing methodology mode of operation, different traditional adders are optioned with certain conditions.
? In the modified reverse converter as compare with the existing reverse converters which are used in Residue Number Systems (RNS) the synthesis functions of various parameters.
? The problem of designing high-performance reverse converters has motivated continuous research using two main approaches to improve the performance of the converters: 1) investigate new algorithms and novel arithmetic formulations to achieve simplified conversion formulas and 2) introduce new moduli sets, which can lead to more simple formulations.
? However, we could address this problem by eliminating the additional prefix level and using a modified excess-one unit instead.
? There is a binary-to-excess-one converter (BEC), which can be modified to fix the double-representation of zero issue.
? This problem can be addressed by eliminating the additional prefix level and using a modified excess-one unit.
• Its real time usage requires forward and reverse converters to be enact as an integrants in the proposed digital systems to fulfill the future requirements in the manufacture analysis of distinct scale of integrations.
• The proposed modified reverse converter is more efficient architecture and lower area with the regular stimuli’s of different adders like HRPX adders, HMPE adders.
• In the proposed design, the main focus was given on the reduction of power delay product with reduced area i.e number of LUTs without compromising the performance as compared to other hybrid prefix architectures.
• In the research and development of innovative arithmetic architectures are enhanced and confined with these proposed methods of reverse converters in RNS formulation.
? The characteristics of the moduli set and conversion algorithm have significant effects on the reverse converter performance.
? In addition to the moduli set, hardware components selection is key to the RNS performance.
? The circuit performance metrics such as area, delay, and power-consumption can be adjusted by selecting the desired prefix structure.
? However, parallel-prefix adders with its high-speed feature have been used in the RNS modular arithmetic channels.
? This leads to significant speed degradation, due to the linear increase of the delay in the RCA with the number of bits. Parallel-prefix adders can be used in the RNS reverse converters to bind the delay to logarithmic growth.
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