A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m)

Abstract : This paper presents a novel low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed scheme can correct m = Dw = 3m/2 -1 multiple error combinations out of all the possible 2m - 1 errors, which is superior to many existing approaches. From the mathematical and practical evaluations, the best case error correction is m/2 bit errors. Tests on 80-bit parallel and, for the first time, on 163-bit Federal Information Processing Standard/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, suggest that it requires only 106% and 170% area overheads, respectively, which is lower than the existing approaches, while error injection-based behavioral analysis demonstrates its wider error correction capability.
 EXISTING SYSTEM :
 ? These advantages are evident from the sheer number of published FPGA-based LDPC decoder designs that exist in the open literature, which will be compared later in this paper. ? Many scheduling variations exist, but the three most common schedules are described here, namely flooding, Layered Belief Propagation (LBP)and Informed Dynamic Scheduling (IDS). ? Several variations of the LDPC decoding algorithm exist. Some algorithms vary from each other only slightly, while others may employ vastly different mathematical concepts. ? This inevitably hinders innovation within the field, since every prospective designer is required to commence by implementing a basic structure, rather than improving an existing design.
 DISADVANTAGE :
 ? The underlying problem of including features for indicating the occurrence of an error to the outside world is that it may also alert an attacker, intent on IP theft, of the circuits internal activity. ? In addition to the size of the factor graph and the degrees of its nodes, the position of the edges within the factor graph also has a significant impact on the associated error correction performance, as well as upon the decoding complexity. ? This could be crudely factored into the results by dividing the processing throughput by the clock frequency, but doing so would then negate the impact of other parameters such as the critical path length.
 PROPOSED SYSTEM :
 • The original LDPC code construction method proposed by Gallager involves stacking Dc number of submatrices on top of each other. • We propose an approximate metric based on the fundamental building blocks of FPGAs, namely the 4LUT and the FF. • In our proposed architecture, two memory blocks are utilized, one for the input LLR values (PMEM) and one for the check to variable messages (RMEM). Assume that all input LLRs and exchanged messages are quantized on bits. • With the proposed CNBP architecture, two minimum values of bit-width, a minimum index of bit-width , and -sign values are stored in RMEM for each decoding layer.
 ADVANTAGE :
 ? A through comparison with other error correction schemes, along with a fully random error injection analysis, have been carried out to validate the performance of the proposed technique. ? The performance of the proposed technique has been analyzed with both bit-parallel and digit-serial multipliers of various complexities over binary extension fields by subjecting them to multiple bit errors. ? In particular, for a realistic measure of the performance, a 163-bit digit-serial multiplier, which is considered to be the standard for Public Key Cryptography set by NIST and FIPS, is also made error tolerant with the proposed technique. ? Bit-parallel multipliers are mainly used in applications requiring very high performance.

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