Energy-Quality Scalable Adders Based on Non-zeroing Bit Truncation
ABSTARCT :
Approximate addition is a technique to trade off energy consumption and output quality in error-tolerant applications. In prior art, bit truncation has been explored as a lever to dynamically trade off energy and quality. In this brief, an innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to stateof-the-art truncation schemes. This translates into energy reduction at a given quality target. When applied to a ripple-carry adder, the proposed bit truncation approach improves quality by up to 8.5 dB in terms of peak signal-to-noise ratio, compared to traditional bit truncation. As a case study, the proposed approach was applied to a discrete cosine transform engine. In comparison with prior art, the proposed approach reduces energy by 20%, at insignificant delay and silicon area overhead.
EXISTING SYSTEM :
? The design with respect to RCA-8 bit from the existing model would improvise the proposed design with an area percentage about 9.3 for RCA8 bit ensuring the larger delay due to extensive forward feed awaiting for carry generation at each stage.
? Increasingly huge data sets and the need for instant response require the adder to be large and fast.
? The traditional ripple-carry adder (RCA) is therefore no longer suitable for large adders because of its lowspeed performance.
? Many different types of fast adders, such as the carryskip adder (CSK), carry-select adder (CSL), and carry-look-ahead adder (CLA), have been developed.
DISADVANTAGE :
? This bit has been implemented by using the given bit values under the RCA implementation. Root Cause Analysis is a useful process for understanding and solving a problem.
? As an analytical tool, RCA is an essential way to perform a comprehensive, system-wide review of significant problems as well as the events and factors has been implemented by using the given values.
? To deal with error-tolerant problems, some truncated adders/multipliers have been reported, but are not able to perform well in its speed, power, area, or accuracy.
? The error-tolerant design can be a potential solution to this problem.
PROPOSED SYSTEM :
• An innovative bit truncation strategy is proposed to achieve more graceful quality degradation compared to state of- the-art truncation schemes.
• When applied to a ripple-carry adder, the proposed bit truncation approach improves quality by up to 8.5 dB in terms of peak signal-to-noise ratio, compared to traditional bit truncation.
• In this paper more than 32 bit has been proposed and they will deliver the output with minimum error.
• This may used the approximate adders process and the application of this purpose is mainly deliver the data with accuracy in Least Significant Bit (LSB).
ADVANTAGE :
? Among the existing techniques with static accuracy, is the most energy efficient as its energy-quality curve lies to the left of the other curves.
? The ETA can attain great improvement in both the power consumption and speed performance.
? If the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved.
? The proposed technique is able to retain the dynamic energy-quality configurability of traditional reconfigurable approximate adders, while achieving more favorable energy-quality tradeoff which trades certain amount of accuracy for significant power saving and performance improvement, is proposed.
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