Gate Diffusion input based 4-bit Vedic Multiplier Design
Abstract : A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.
? In existing, a brand new logic formulation for RCA is planned to support the most use of complementary (AOI/OAI) gates within the crucial path for delay minimization.
? In this paper, GDI based Vedic Multiplier is designed along with existing adder circuits are simulated in SPICE tool. Power, delay, transistor count and PDP is compared for circuit optimization.
? The proposed Vedic multiplier overcomes the disadvantages of the existing Vedic multiplier, by reducing the area of complexity of the circuit and also reduces time delay, so thereby improving the speed of operation.
? The design of the Vedic multipliers using novel adder which uses GDI technology is explained and is further compared with the existing CMOS technology.
? They are also applicable to complex problems involving a large number of mathematical operations.
? GDI logic suffers from the issue of reduced signal swing at the output.
? In the era of nanoscale CMOS, radiation-induced soft errors became a heavy issue at ground level.
? The planned structure may be reconfigured for various filter lengths with negligible overhead quality and it supports variable convergence issue.
? A new low power design technique that solves most of the issues proverbial as Gate-Diffusion Input (GDI) is planned.
• In this paper, proposed 4-bit Vedic multiplier using Gate Diffusion Input (GDI) is presented.
• The proposed GDI full adders are simulated using MICROWIND with 90nm technology with supply voltage ranging from 1V.
• In the operation and theatrical analysis of the proposed Vedic multiplier using novel adder has been carried out.
• The proposed Vedic multiplier using novel adder based on the GDI technology is much better than the Vedic multiplier supported by conventional CMOS logic scheme.
• The area of complexity of the proposed Vedic multiplier based on GDI technique is reduced by 73.59% when considered to the Vedic multiplier supported by conventional CMOS logic scheme.
? In any digital system design, the three main performance parameters that determine the performance of the system are speed, power, and area.
? The circuit level, an appropriate choice of logic design such as the classical complementary metal oxide semiconductor (CMOS), a transmission gate, or a novel gate diffusion input (GDI) can be explored to minimise the performance parameters.
? The performance of both implementations in terms of average power dissipation and TC is analysed.
? The FPGA implementations of these architectures have already been found efficient in terms of delay and circuit complexity when compared with the conventional multipliers.
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