Graph-Based Transistor Network Generation Method for Super gate Design
Abstract : Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series–parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.
? Existing graph-based methods, in turn, are able to provide the NSP solution, also with seven transistors.
? However, there exist efficient heuristics to deal with the problem and to obtain acceptable orders in a reasonable CPU execution time.
? All new transistors created during the duplications can be stored in the existing transistor list and no new structure is necessary to keep the modifications.
? The existence of parasite elements (capacitances and resistances) impacts directly in the electrical signal propagation on the circuits.
? A transient on input signal, there will be a period in which both NMOS and PMOS transistor will conduct simultaneously, causing a current flow through the direct path existing between power supply and ground terminals.
? There are other parameters that impact circuit quality such as transistor sizing, layout compaction, and waveform of input stimuli.
? The drawback for generating this kind of network is that complementary series/parallel operations cannot be used to obtain the dual plane, since there are some transistors that are neither in series nor in parallel with others.
? The disadvantages of fullcustom can include increased manufacturing and design time, and much higher skill requirements on the part of the design team.
? The disadvantage is that the constrained nature of the library, especially due to the limited number of cells, reduces the possibility of finetuning the design.
• The proposed method starts from a sum-of products (SOP) form F and produces a reduced transistor network.
• The Vdd/Gnd and Output nodes are kept as special vertices (this information is necessary in the proposed algorithm).
• It is important to notice that the solution proposed here does not generate transistor networks from an equation description, as it is done in state-of-the-art transistor networks generation methods.
• The work proposed here concentrate at the cell level, and investigates more efficient area and delay methods to optimize transistor networks taking into account the length of chains and the overall transistor counts.
? In this sense, one can consider the bounded solution when targeting performance or the unbounded solution for smaller area.
? Therefore, efficient algorithms to automatically generate optimized transistor networks are quite useful for designing digital integrated circuits (ICs).
? Even though previous steps are very efficient in finding logic sharing, there may still cubes not represented through any of the found networks.
? Switch based technologies, such as CMOS, FinFET, and carbon nanotubes, can take advantage of such an improvement.
? The nMOS transistor width is 64 nm while the pMOS transistor width is defined using the PN ratio equals to two, in the inverter gate used as reference for the logical effort method.
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