Low-Power Approximate Unsigned Multipliers with Configurable Error Recovery
ABSTARCT :
Approximate circuits have been considered for applications that can tolerate some loss of accuracy with improved performance and/or energy efficiency. Multipliers are key arithmetic circuits in many of these applications including digital signal processing (DSP). In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery circuit. The approximate multipliers using these two error reduction strategies are referred to as AM1 and AM2, respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Wallace multiplier optimized for speed, an 8×8 AM1 using four most significant bits for error reduction shows a 60% reduction in delay (when optimized for delay) and a 42% reduction in power dissipation (when optimized for area). In a 16×16 design, half of the least significant partial products are truncated for AM1 and AM2, which are thus denoted as TAM1 and TAM2, respectively. Compared with the Wallace multiplier, TAM1 and TAM2 save from 50% to 66% in power, when optimized for area. Compared with existing approximate multipliers, AM1, AM2, TAM1, and TAM2 show significant advantages in accuracy with a low power-delay product. AM2 has a better accuracy compared with AM1 but with a longer delay and higher power consumption. Image processing applications, including image sharpening and smoothing, are considered to show the quality of the approximate multipliers in error-tolerant applications. By utilizing an appropriate error recovery scheme, the proposed approximate multipliers achieve similar processing accuracy as exact multipliers, but with significant improvements in power.
EXISTING SYSTEM :
? In existing system, a approximate multiplier with low power and small critical path is deliver for high performance DSP applications.
? To Reduce the Delay of the Existing Circuitry we implemented another method where we have less area and delay compared to existing technique of approximation.
? It has been shown that this may lead to low accuracy, because errors may accumulate and it is difficult to correct errors using existing approximate adders.
? The adders in each layer operate in parallel without carry propagation, and the same operation repeats until two rows of partial products remain.
DISADVANTAGE :
? Longer delay
? High power consumption
? Low accuracy
? Only luminance multiplication is achieved ( Gray Scale )
? Errors in the final product.
PROPOSED SYSTEM :
• In the proposed approximate multiplier, a simple tree of the approximate adders is used for partial product accumulation and the error signals are used to compensate errors for obtaining a better accuracy.
• The proposed approach decreased the number of vertical product terms in the PPM with the aim of reducing the height of the critical column in the accumulation tree.
• The proposed multiplier organizes the partial product terms using different sizes of significant driven logic clusters.
• The proposed designs can be used as effective library cells for the synthesis of approximate circuits.
ADVANTAGE :
? These applications, approximate circuits play an important role as a promising alternative for reducing area, power and delay, thereby achieving better performance in energy efficiency.
? In, the error distance (ED) and mean error distance (MED) are proposed to evaluate the performance of approximate arithmetic circuits.
? Moreover, the PDP and area-delay product (ADP) are calculated to better assess performance at the circuit level.
? The performance of each approximate multiplier, image multiplication is selected because it directly employs multiplication without any other operations.
? In Digital Signal Processing (DSP), which performance improved with loss of accuracy for application of approximate circuits.
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