Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
Abstract : Design of a low-energy power-ON reset (POR) circuit is proposed to reduce the energy consumed by the stable supply of the dual supply static random access memory (SRAM), as the other supply is ramping up. The proposed POR circuit, when embedded inside dual supply SRAM, removes its ramp-up constraints related to voltage sequencing and pin states. The circuit consumes negligible energy during ramp-up, does not consume dynamic power during operations, and includes hysteresis to improve noise immunity against voltage fluctuations on the power supply. The POR circuit, designed in the 40-nm CMOS technology within 10.6-µm2 area, enabled 27× reduction in the energy consumed by the SRAM array supply during periphery power-up in typical conditions.
? It is noteworthy that in some cases there exist limit cycle trajectories that does not satisfy the latter condition yet are asymptotic.
? This criteria is based on the existence of at least two periodic solutions for a periodically accessed SRAM cell.
? Moreover, it has been shown that the behavior of the infinitely long chain of the noisy gates can be investigated by analyzing a loop comprising the noisy gates of the chain.
? In other words, for any noise source the noise margin is the amount of noise that makes the cell violate the criteria of data stability: having three coincident points on VTC and its mirror.
? In the event that the ISO stick requirement is does not achieve, a unauthentic problem happens starting the steady source VA when VP remains high.
? Therefore, novel efficient techniques needs to be investigated along with the feasibility of the conventional schemes to alleviate this problem.
? The dynamic power consumption of the SRAM units is becoming an issue as the technology scales.
? The FSM starts its operation upon receiving the activation signal which is issued by the interface circuitry.
• The proposed circuit is distinguishes the increase in fringe voltage utilizing exhibit voltage.
• The yield motion OUT can be utilized as the isolation signal, to guarantee that here is no immediate way between the VA& the shared belief amid VP increase.
• In the proposed architecture, selective variation of the source voltage of the drive transistors breaks the deadlock between the standby power consumption and the dynamic power consumption.
• The proposed definition of the dynamic data stability criteria introduces a new bound for the cell parameter variations and revises the notion of static noise margin (SNM).
? To measure its efficiency, the proposed POR was integrated with the netlist, along with parasitics, of an SRAM instance in the same technology.
? The output signal OUT can be used as the ISO, to ensure that there is no direct path between the VA and the common ground during VP ramp-up.
? It requires less power to operate.
? High performance.
? It requires less voltage levels.
? It reduce leakage current.
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