Pre-charge-Free, Low-Power Content-Addressable Memory
ABSTARCT :
Content-addressable memory (CAM) is the hardware for parallel lookup/search. The parallel search scheme promises a high-speed search operation but at the cost of high power consumption. Parallel NOR- and NAND-type matchline (ML) CAMs are suitable for high-search-speed and low-power-consumption applications, respectively. The NOR-type ML CAM requires high power, and therefore, the reduction of its power consumption is the subject of many reported designs. Here, we report and explore the short-circuit (SC) current during the precharge phase of the NOR-type ML. Also proposed here is a novel precharge-free CAM. The proposed CAM is free of the drawbacks of the charge sharing in the NAND and the SC current in the NOR-type CAM. Postlayout simulations performed with a 45-nm technology node revealed a significant reduction in the energy metric: 93% and 77% lesser than NOR- and NAND-type CAMs, respectively. The Monte Carlo simulation for 500 runs was performed to ensure the robustness of the proposed precharge-free CAM.
EXISTING SYSTEM :
? The proposed and existing CAM ML architectures were developed using CMOS 45nm technology node with a supply voltage of 1 V.
? If all the bits in a row are matched with input search word, then no pull-down path exists for the ML and hence, it retains its precharged value.
? The advantage of using parity as a parameter is that parameter memory is highly reduced comparison with existing systems as only one bit i.e. k=1 is required for storing parameter corresponding to each stored word whatever may be the length of input data bits.
? The pull-down transistors arranged in NOR type is beneficial for search performance, but they contribute a lot of drain capacitances to the ML.
DISADVANTAGE :
? Due to the serially connected pass transistors along the ML, charge sharing problem occurs and limits the length of the word.
? The proposed CAM is free of the charge-sharing problem, as there are no serial pass transistors along the ML and, as shown in the following text, gives freedom in choosing any number of bits in a word.
? NAND-type ML is not preferred for CAMs with long words because of the large delay, and also it suffers from charge sharing problem across the pass transistors.
? A novel CAM ML technique is proposed that is free of precharge logic, SC current, and charge sharing problem.
PROPOSED SYSTEM :
• In the proposed architecture, there is no need of frequent charging and discharging of matchline.
• The proposed 2bit TCAM is also simulated with the help of cadence and noticed that it takes 20% lesser power than the traditional.
• We propose a hybrid self controlled precharge-free (HSCPF) CAM architecture, which overcomes the search delay problem of PF CAM and power consumption problem of SCPF CAM.
• The proposed HSCPF CAM overcomes the cascaded ML structure of PF CAM and increased transistor count of SCPF CAM, thereby offering lower energy metric when compared to SCPF CAM and PF CAM.
ADVANTAGE :
? Dual feedback positive sense amplifiers were used to improve performance as well as save energy by the early termination of discharging ML.
? The proposed CAM design improves performance by overcoming the traditional “precharge all and discharge all but one matchline” policy.
? The performance metric averaged across 500 MC runs of proposed CAM shows a 2.7% increase in search delay over the NOR-type and 28.76% lower power consumption than the NAND-type CAM.
? All the existing CAM employ NOR- or/and NAND-type CAM for their basic ML, it is possible to replace the basic ML (NOR and NAND type) in those architectures with the proposed CAM design to attain improved performance.
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