TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
Abstract : A scalable approximate multiplier, called truncation- and rounding-based scalable approximate multiplier (TOSAM) is presented, which reduces the number of partial products by truncating each of the input operands based on their leading one-bit position. In the proposed design, multiplication is performed by shift, add, and small fixed-width multiplication operations resulting in large improvements in the energy consumption and area occupation compared to those of the exact multiplier. To improve the total accuracy, input operands of the multiplication part are rounded to the nearest odd number. Because input operands are truncated based on their leading one-bit positions, the accuracy becomes weakly dependent on the width of the input operands and the multiplier becomes scalable. Higher improvements in design parameters (e.g., area and energy consumption) can be achieved as the input operand widths increase. To evaluate the efficiency of the proposed approximate multiplier, its design parameters are compared with those of an exact multiplier and some other recently proposed approximate multipliers. Results reveal that the proposed approximate multiplier with a mean absolute relative error in the range of 11%–0.3% improves delay, area, and energy consumption up to 41%, 90%, and 98%, respectively, compared to those of the exact multiplier. It also outperforms other approximate multipliers in terms of speed, area, and energy consumption. The proposed approximate multiplier has an almost Gaussian error distribution with a near-zero mean value. We exploit it in the structure of a JPEG encoder, sharpening, and classification applications. The results indicate that the quality degradation of the output is negligible. In addition, we suggest an accuracy configurable TOSAM where the energy consumption of the multiplication operation can be adjusted based on the minimum required accuracy.
? The delay of the proposed multipliers has reduced greatly, almost ten times less in the case of 32-bit width multiplier compared to the existing 32-bit multiplier mentioned.
? A comprehensive comparison of the existing approximate multipliers has been performed on 8-bit designs.
? The segment-based multipliers are very competitive in terms of both power and area, while the other designs have at least one major shortcoming in accuracy, delay or power.
? The dual segmentation approximate multiplier achieves better performance in terms of the delay, area and energy compared to the DSM-based multiplier while having almost the same accuracy level as the DSM-based multiplier.
? The adders used for arithmetic binary operations have a major impact on the performance parameters in any processing unit.
? To evaluate the impact of changing the multiplier size, each multiplier is exploited to design 16-bit and 32-bit multipliers.
? Multiplication is a fundamental high-energy operation in image processing and deep learning applications.
? Prior works have explored different techniques to reduce the cost of multiplication using approximate multipliers.
? This multiplier design is appliable to both signed and unsigned multiplications and is constructed by modifying the conventional multiplication method at the algorithm level.
• The proposed design, multiplication is performed by shift, add, and small fixed-width multiplication operations leading to large enhancements within the energy consumption and area occupation compared to those of the exact multiplier.
• Moreover, the proposed approximate multiplier has a nearly normal error distribution with near zero mean value.
• The proposed multiplier was scalable and outperformed other approximate multipliers in terms of speed, area, and energy.
• The proposed 32-bit multiplier, on average, improved the energy consumption 95% compared to the exact Wallace multiplier while occupied 85% less area.
? These simplifications result in higher accuracy and performance compared to those of the state-of-the-art approximate multipliers.
? An algorithm was suggested to design efficient approximate multipliers composed of these compressors.
? In the Arithmetic Unit, some of the adders and logical AND gates should be power gated based on the operating mode to make the design more power efficient.
? To assess the efficacy of the proposed multipliers, we have exploited them in different image processing applications such as sharpening and the JPEG image compression.
? To estimate the efficacy of the proposed approximate multiplier in classification applications, we have trained a neural network offline with 50 hidden neurons for the MNIST data set.
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