VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding
Abstract : For multiplier dominated applications such as digital signal processing, wireless communications, and computer applications, high speed multiplier designs has always been a primary requisite. In this paper a high performance 64x64 bit redundant binary (RB) multiplier have been designed by using recently proposed redundant binary encoding approach to eliminate the error correcting word and a delay efficient parallel prefix Ling adder for final redundant binary to normal binary (RB-NB) conversion. Since redundant binary (RB) representation allows carry-free addition and adaptability, it has been used in 64x64 bit high-performance RB multiplier design for summation of partial product terms. The design of multiplier also reduces redundant partial product accumulation stage when eliminating the error correcting word which improves the complexity and the critical path delay. The performance of RB multiplier design compared with conventional RB modified booth encoding multiplier (CRBMBE). The comparison is based on synthesis result obtained by synthesizing both multiplier architectures targeting a Xilinx FPGA in terms of area and delay analysis.
? In fast digital multiplier design, modified Booth encoding algorithm is an efficient way to reduce the number of partial products by grouping consecutive bits in one of the two operands to form the signed multiples.
? Modified Booth Encoding (Radix-4) can adequately be connected to lessen the quantity of incomplete item columns to half in parallel multipliers.
? In order to overcome the overheads of existing Booth encoding algorithms, covalent redundant binary Booth encoding was used.
? By removing hard multiples in the Digital multiplier of the processor, Digital multiplier will perform much faster than existing method.
? In this paper a high performance 64x64 bit RB multiplier has been designed, using preceding techniques to overcome the problems in traditional multiplier design.
? A radix-16 RB Booth encoder can be used to overcome the hard multiple problem and avoid the extra ECW, but at the cost of doubling the number of RBPP rows.
? A new radix-16 Booth en-coding (RBBE-4) technique without ECW has been pro-posed; it avoids the issue of hard multiples.
? When we go for higher adders the time is increases due to complexity and irregularity.
• The proposed method overcomes the hard multiple generation problem of NB Booth encoders without incurring any correction vector.
• Several techniques to achieve RB-NB conversion hasbeen proposed, which has the advantage over CLA’s.
• Many algorithms and architectures have been proposed to design high-speed and low-power multipliers.
• The proposed designs achieve significant reductions in area and power consumption compared with existing multipliers when the word length of each of the operands is at least 32 bits.
• The proposed RBMPPG-2 can be applied to any bit RB multipliers with a reduction of a RBPP accumulation stage compared with conventional designs.
? To accelerate the overall performance of the systems, designing high performance multipliers has always been one of the main objectives for system designers.
? To achieve the multiplication process more efficiently, numerous high performance algorithms and architectures have been proposed.
? This paper presents a high performance 64x64 bit Redundant binary multiplier with modified redundant binary partial product generator, RB summing tree, and 128 RB to NB Converter.
? The Power delay product is a commonly used metric for combined performance in terms of delay and power consumption.
? It is one of the most useful methods for designing an area efficient RB MBE multipliers with power-of-two word length.
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