Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
Abstract : Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = -Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 × 16 and 32 × 32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
? It uses a fixed supply voltage and clock period and will reduce the manufacturing cost incurred by existing NBTI-tolerant techniques.
? The existing array multiplier is well known due to its regular structure and multiplier circuit is based on add and shift algorithm.
? The existing column bypassing multiplier is a modification of normal array multiplier and here the full adder is always active regardless of input states.
? The existing column bypass multiplier uses fixed latency design, which will hold the clock signal for one clock cycle when there is an error, and hence there by increasing the delay.
? To avoid this problem, many NBTI-aware methodologies have been proposed. An NBTI-aware technology mapping technique was proposed into guarantee the performance of the circuit during its lifetime.
? The impact of frequency is relatively insignificant, the effect of signal frequency is ignored.
? When the biased voltage is eliminated, the opposite response occurs, reducing the NBTI impact.
? In process-variant tolerant structure for mathematics units was proposed, where the impact of process variation is considered to growth the circuit yield.
• They proposed an NBTI optimization technique that taken into consideration path sensitization.
• A training scheduling set of rules changed into proposed into schedule the operations on non-uniform latency practical devices and enhance the overall performance of Very long instruction word processors.
• An aging-aware reliable multiplier method that is appropriate for huge multipliers. Despite the fact that the test is accomplished in 4-, 8-, 16- and 32-bit multipliers, our proposed architecture can be effortlessly prolonged to big designs.
• Our proposed AHL circuit can accurately expect whether or not the input patterns require one or two cycles in most instances.
? The throughput of these applications depends on multipliers, and if the multipliers are too slow, the performance of entire circuits will be reduced.
? A short path activation function algorithm was proposed in to improve the accuracy of the hold logic and to optimize the performance of the variable-latency circuit.
? These research designs were able to reduce the timing waste of traditional circuits to improve performance, but they did not consider the aging effect and could not adjust themselves during the runtime.
? The maximum path delay for all paths will cause significant timing waste for shorter paths, and redesigning the multiplier with variable latency can improve their performance.
|