Resource-Efficient SRAM-based Ternary Content Addressable Memory
ABSTARCT :
Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A 72 × 28-bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM).
EXISTING SYSTEM :
? All other existing TCAMs energizes the entire SRAM memory for searching each incoming TCAM word.
? This system activates a part of SRAM memory for lookup instead of activating the entire SRAM memory, so power consumption is less compared to other architectures.
? These stores the TCAM word’s existence and address information separately in distinct sets of SRAM blocks.
? The Input TCAM word is applied to the first set of SRAM blocks to read its existence information and the address information is read from the second set of SRAM blocks.
? The existing SRAM-based TCAM architectures energize the entire SRAM memory of their architectures, resulting in excessive power consumption.
DISADVANTAGE :
? It possesses size issues, issues of memory overflow and also it can?t provide a deterministic operation.
? The increase in the number of TCAM sub-tables M has a decreasing impact on the size of the activated BRAM resource in the proposed EE-TCAM design.
? This paper proposes a custom low power dynamic TCAM using nano electromechanical (NEM) relay devices utilizing one-shot refresh to solve the memory refresh problem.
? The CMOS dynamic TCAM (DTCAM) is denser but suffers from refresh problems in latency and energy. Nonvolatile TCAM can be achieved by STT-MRAM, RRAM, FeFET, etc
PROPOSED SYSTEM :
• Parallel Hashing Memory proposed is a memory architecture which is an alternative to content addressable memory.
• Scalable TCAM proposed in has a Scalable and modular architecture with multiple optimizations.
• The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word.
• The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word, thus attaining a substantial reduction in the overall dynamic power consumption.
• This is achieved by partitioning the large width TCAM bit patterns and then implementing them as a cascade of SRAM blocks in the proposed architecture.
ADVANTAGE :
? To the best of our knowledge, this is the first work to show relationships among the performance parameters embedded as a part of the TCAM emulation architecture.
? It has high production cost per bit of memory storage and exhibits less storage efficiency than SRAM devices of comparable bit density and access time.
? This brief focuses on efficiently using resources, such as memory and throughput, and proposes a resource-efficient SRAM-based TCAM (REST) emulation architecture to make use of memory–throughput tradeoff in SRAM-based TCAM.
? The REST memory architecture makes use of VBs in the SRAM units to achieve memory efficiency at the cost of reduced throughput.
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