A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
Abstract : In this paper, a double-error-correcting and tripleerror-detecting (DEC-TED) Bose–Chaudhuri–Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%–48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4–10-2 raw bit-error rate.
? The maximum clock speed of the decoder is limited by the process technology and the complexity of the decoder.
? A useful property of the syndromes is that if all calculated syndromes are zero, then no errors exist in the received message.
? This makes it possible to only calculate a limited set of syndromes, and then apply the relations to expand them into the full set of syndromes. This decreases the overall area and power requirements of the decoder.
? Information theory tells us that coding systems exist that allow us to use noisy communication channels reliably.
? The emerging memories are fighting with diminished reliability, when the memory scales down, as a solution for this problem error-correcting code and its encoder or decoder circuits have developed.
? The adaptive error correction gives high decoding efficiency and invalid transition technique reduce the power consumption issue in conventional BCH decoders.
? When continuously non error code words are entered into the decoder, the impact of invalid transition in the power consumption is strong.
? When a non-error code word is appeared on decoder, the syndrome-coefficient of reverse error location polynomial- and error vector are settled to 0.
• In this paper, an encoder and decoder system is proposed using (BCH) double error-correcting and triple-error detecting (DEC-TED) with emerging memories of low power and high decoding efficiency.
• The proposed invalid transition inhibition techniques and adaptive error correction are applied to the decoder.
• A particular clock called the Error Correcting Clock (ECC clock) is adopted in the decoder to bring about the control signals.
• The proposed LLC has a new reading circuit with a dualsensing redemption scheme that improves STTMRAM performance along with standard error correction code (ECC).
? In this paper, we propose a high-decoding-efficiency and low-power BCH decoder with DEC and triple-error-detecting (DEC-TED) capability for emerging memories.
? To simply increasing the memory yield, ECC can be used to optimize memory performance regarding density and energy consumption.
? As non- or single-bit errors are considerably more likely than multibit (double-bit or triplebit) errors despite the increased raw bit-error rate (RBER) in nanotechnology, it is inefficient to deal with non- or singlebit errors with a DEC-TED decoder in terms of latency and power, which leads to reduced decoding efficiency.
? A DEC-TED BCH decoder using an adaptive error correction and an invalid transition inhibition technique is proposed to achieve the high decoding efficiency and low-power consumption.
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