A Low-Power Architecture for the Design of a One-Dimensional Median Filter
Abstract : This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced.
? When an input sample enters the window, the sorting of existing samples is reused in generating the new median output.
? The proposed median filter offers comparable search performance, scalability and lower cost than existing median filter.
? Short-circuit current exists during the transitions as one network is turned on and the other network is still active.
? The delay increases significantly as the voltage approaches the threshold voltage and the capacitance load for routing and/or pipeline registers increases, there exists an optimal power supply voltage.
? To conquer this problem, a new median filter architecture targeting low power consumption is proposed.
? The main problem of the median filter is its high computational cost: the temporal complexity of sorting N values even with the most efficient sorting algorithms is O(N•log N).
? The low power design problems can be broadly classified into two: analysis and optimization. Analysis problems are concerned about the accurate estimation of the power or energy dissipation at different phases of the design process.
? But major criteria to be considered are the impact of circuit delay which affects throughput and performance of circuit.
• A modified selective one dimensional median filter design is proposed in this work which is aimed at reducing the power consumption.
• In this paper, an efficient design of median-filter hardware, capable of delivering the median value in real-time under stringent requirements on power is proposed.
• A new word level one dimensional filter architecture is proposed, in which the new median output, with a filtering latency of only one clock cycle, is generated at each machine cycle for each incoming sample.
• The improvement is achieved by performing the deletion and insertion of samples in one clock cycle, and a new control circuit is proposed to govern these two operations.
? A median filter is a nonlinear filter widely used in digital signal and image processing for the smoothing of signals, suppression of impulse noise, and edge preservation.
? The performance of imaging sensors is affected by a variety of factors, such as environmental conditions during image acquisition and by the quality of sensing elements themselves.
? There is great interest in understanding how to continue increasing performance without increasing the power dissipation.
? With the advent of internet technology and the stupendous growth of multimedia technologies, the design of power efficient real time image and video processing hardware has become a great challenge to designers and researchers.
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