Approximate Sum of Products Designs Based on Distributed Arithmetic
Abstract : Approximate circuits provide high performance and require low power. Sum-of-products (SOP) units are key elements in many digital signal processing applications. In this brief, three approximate SOP (ASOP) models which are based on the distributed arithmetic are proposed. They are designed for different levels of accuracy. First model of ASOP achieves an improvement up to 64% on area and 70% on power, when compared with conventional unit. Other two models provide an improvement of 32% and 48% on area and 54% and 58% on power, respectively, with a reduced error rate compared with the first model. Third model achieves the mean relative error and normalized error distance as low as 0.05% and 0.009%, respectively. Performance of approximate units is evaluated with a noisy image smoothing application, where the proposed models are capable of achieving higher peak signalto-noise ratio than the existing state-of-the-art techniques. It is shown that the proposed approximate models achieve higher processing accuracy than existing works but with significant improvements in power and performance.
? The non-decomposed LUT the proposed design achieves significant savings in area and power over the best existing scheme.
? It is ordinarily realized that every second any processors performed a large number of work works in semiconductor industry.
? More and more technologies with lot of features and advantages are arising. Reversible logic is one such emerging concept. One of the main characteristics of reversible circuits is their less power consumption.
? The synthesis results showed that the proposed reconfigurable FIR filter can operate at high speed consuming minimum area and power.
? The contamination of a signal of interest by other unwanted signal or noise is a problem often encountered in many applications.
? The adder used at this stage is a floating point adder, issues like rounding and normilization will be considered in its implementation.
? The speed and range are presently the very beginnings of the principal configuration issues in advanced period.
? While this cross sections well with symmetric limit taking care of strategies for entire specimen symmetric (odd-length) direct stage channels, there are blocks with half-example symmetric (evenlength) channels, a reality that impacted the JPEG 2000 standard.
• In this paper, we propose a method for outlining of FIR channel utilizing multiplier in light of compressor and convey select viper.
• Various proposed Distributed Arithmetic method for reduction of area, delay and power.
• The proposed architecture is composed of three modules namely DA filter module, auxiliary LUT and the controller module.
• . The algorithm proposed has lowest power requirement, whereas the algorithm proposed by has lowest area requirement.
• The proposed scheme has reduced the LUT size to half by storing the offset-binary-coding (OBC) combinations of filter weights and input samples.
? Approximate computing provides an efficient solution for the design of power efficient digital systems.
? Distributed arithmetic is a very efficient means for calculation of the inner products between vectors.
? It requires no multiplication and it has an efficient mechanism to perform the SOP operation.
? The main advantage of distributed arithmetic is its high computational efficiency.
? Distributed arithmetic is a popular technique for implementing the SOP computations without the use of multipliers. SOP units based on the distributed arithmetic are frequently used in filters and other DSP applications.
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