A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme
Abstract : This paper presents a 12-bit 40-MS/s successive approximation register analog-to-digital converter (ADC) for ultrasound imaging systems. By incorporating a fast binary window digital-to-analog converter (DAC) switching technique, the problematic most significant bit transition glitch was removed to improve linearity without increasing the input capacitance or using a calibration scheme. A hybrid DAC was also developed to overcome the yield problem that occurs when a tiny unit capacitance is used in the DAC. Moreover, a reference buffer was used to accelerate the DAC settling to achieve highspeed conversion. The prototype ADC was fabricated using a 130-nm CMOS technology. The ADC core occupied an active area of 0.1 mm2 and consumed a total power of 1.32 mW when a 1.2-V supply was used at a conversion rate of 40 MS/s. The measured peak signal-to-noise-and-distortion ratio and spuriousfree dynamic range were 64 and 77.5 dB, respectively. The peak effective number of bits was 10.33, which is equivalent to a Walden figure-of-merit of 25.6 fJ/conversion step.
? In our design, two design parameters exist, which are the RSC and the CREF. The dynamic performance of a behavioral simulation for a 12-bit SAR ADC according to CREF and the RSC.
? Due to the process variation, mismatch and hysteresis can exist in the comparator because of the use of transistors M13 and M16.
? Therefore, to minimize the hysteresis common centroid layout is used. To reduce the kickback noise and common mode dependent offset calibration the proposed comparator is designed.
? The implemented bootstrap switch operates at the supply voltage. The gate body voltage (VGB) of transistor M11 will be twice the supply voltage.
? To alleviate the power consumption problem of the ADC driver, an input capacitance of only 1.48 pF was used.
? To alleviate the switching energy problem of the DAC part, the proposed switching method which employs CMCR switching technique is implemented in CDAC part.
? A mutated dynamic latch comparator with cascode is implemented to make certain a high speed operation with low power consumption and to overcome the kick back issue.
? Several issues have been considered during the comparator designing such as; due to the comparator’s clock operation, kickback noise affects the CDAC top plate.
• In order to reduce the performance degradation resulting from a signal-dependent voltage drop in a capacitive reference driver (CRD) without increasing the capacitance (CREF) of a CRD, the proposed SCRD utilizes the CRD for LSB conversion cycles.
• In the proposed SCRD, the slight difference between the two reference voltages can be recovered by the redundancy, but it is preferable to use most of the redundancy range for correcting the decision errors before the RSC, which reduces the requirement of an on-chip decoupling capacitor to suppress the large supply fluctuation.
• The proposed SCRD can remove the additional reference drop caused by the MSB parasitic capacitor for the RSC at the third cycle or higher.
? To enhance the operation performance of the reference buffer, the buffer is implemented using a source follower with two resistor strings to yield the sub reference voltages.
? The advantages of successive approximation register (SAR) analog-to-digital converters (ADCs) have been demonstrated to include high energy efficiency and small footprints through the use of thin CMOS technologies.
? In this paper, the proposed SAR ADC was designed to achieve superior energy efficiency for portable ultrasound imaging systems.
? In comparison with previously proposed ADCs that utilize 90–180-nm CMOS technologies, the proposed ADC exhibits a superior energy efficiency.
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