In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
Abstract : This brief proposes an on-line transparent test technique for detection of latent hard faults which develop in firstinput firstouptput buffers of routers during field operation of NoC. The technique involves repeating tests periodically to prevent accumulation of faults. A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic. The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware. In addition, an on-line test technique for the routing logic has been proposed which considers utilizing the header flits of the data traffic movement in transporting the test patterns.
? The faults considered in this brief, if applied for SRAMs or DRAMs, can be detected using standard March tests.
? However, if the same set of faults are considered for SRAM-type FIFOs, March test cannot be used directly due to the address restriction in SRAM-type FIFOs mentioned in and thus we were motivated to choose single-order address MATS++ test (SOA-MATS++) for the detection of faults considered in this brief.
? The transparent SOA-MATS++ algorithm is intended for test of stuck-at fault, transient fault, and read stuck-at fault, transition fault, and read disturb fault tests developed during field operation of FIFO memories.
? The NoC core testing problem is formulated as a unicast-based multicast problem in order to decrease test data delivery time in the NoC.
? Such problems are expected to further worsen with technology scaling.
? Mediator is utilized to take care of the issue of various solicitations coming at single yield port.
? However, test initiation after the buffer gets full would cause the following problems.
? These two problems can be avoided by periodically testing the FIFO buffers. Periodic testing of a FIFO buffer allows test of a different set of locations of the FIFO buffer in each test burst.
• The on-line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NoC and also propose fault tolerant solution by introducing shared buffer in router.
• This proposes an on-line transparent test technique for detection of latent hard faults which develop in first input first output buffers of routers during field operation of NoC.
• A prototype implementation of the proposed test algorithm has been integrated into the router-channel interface and on-line test has been performed with synthetic self-similar data traffic.
• The proposed transparent test is utilized to perform online and periodic test of FIFO memory present within the routers of the NoC.
? The performance of the NoC after addition of the test circuit has been investigated in terms of throughput while the area overhead has been studied by synthesizing the test hardware.
? They can decrease the probability of routing packets through congested areas and thus improve the performance.
? The structure is easy implementation and has a low influence on the performance of PLL.
? Rerouting might take place through non minimal paths which affect the performance significantly not only by taking long paths but also by creating hotspot around a fault.
? The transparent test algorithm is then used to implement a transparent BIST.
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