An Analog LO Harmonic Suppression Technique for SDR Receivers
Abstract : A low-complexity analog technique to suppress the local oscillator (LO) harmonics in software-defined radios is presented. Accurate mathematical analyses show that an effective attenuation of the LO harmonics is achieved by modulating the transconductance of the low-noise transconductance amplifier (LNTA) with a raised-cosine signal. This modulation is performed through the bias network of a cascode device with a negligible increase in the LNTA noise figure. The proposed technique results in a notch at the third harmonic and at least 36 dB of attenuation at the fifth and the seventh harmonics. Experimental results in 130-nm CMOS and postlayout simulation results in 65-nm CMOS verify the proper functionality of the proposed technique and the accuracy of the proposed analyses.
? The digitally enhanced HR approach is indeed a powerful one; it produces unprecedented HR figures, irrespective of (small) analog mismatches that exist in the analog front-end.
? The existence of mismatch (random and systematic) in weighting coefficients, LO generation circuitry, downconversion mixers and eventually layout routings is inevitable particularly at lower technology nodes and higher frequencies.
? Many of the existing modulation schemes naturally lend to such frequency decomposition (e.g., OFDM).
? The high output impedance of the following switching mixer amplifies the wanted channel, while the blocker suppression is realized by designing this output impedance to be low outside of the wanted channel, where the blocker exists.
? The base-band AC coupling has an important impact on the DC offset of the receiver.
? To avoid self-mixing issue at the baseband, we used simple high pass filters prior to digital sampling.
? To understand the impact of the receiver noise performance on the overall array energy efficiency, we will compare the transmitter (TX) and the receiver (RX) behavior in large arrays.
? To minimize the leakage of the pmos devices when turned off, high-threshold devices are used. It was tested that even for FF corner (lowest threshold voltage) the leakage is small enough to have a negligible impact on the waveform at the lowest frequency of 1GHz.
• We propose a digitally enhanced HR architecture exploiting digital adaptive interference cancelling (AIC).
• An analog two-stage polyphase HR concept is proposed to greatly enhance the amplitude accuracy for both third and fifth harmonics so that the total amplitude error becomes product of errors.
• To improve resilience of such receivers to LO harmonic interferers, a digitally-assisted dual-path receiver with nonuniform LO phases is proposed which employs an adaptive digital equalizer to suppress distortion products.
• In the proposed 4-phase dual-path receiver, the MMSE equalizer minimizes the LO harmonic distortion while accounting for the noise correlation among the polyphase paths to achieve high HRR and low NF values.
? If the harmonic interferer statistics remains approximately constant, which can be readily measured by monitoring changes in the covariance matrix elements that is constantly updated based on each digitized samples, the equalizer coefficients need not be changed and one-time calibration would be sufficient.
? Although this tuning process is foreground and should be performed during the startup, similar to many other foreground tuning techniques, the temperature can affect the tuned coefficients.
? The single and joint harmonic matching performance of a zero-IF M-phase mixer-first receiver is analyzed.
? Digital compensation of harmonic distortion is employed to achieve robust and high-performance harmonic rejection.
|