Byte-Reconfigurable LDPC Codec Design With Application to High Performance ECC of NAND Flash Memory Systems
ABSTARCT :
The reliability of NAND Flash memory deteriorates due to multi-level cell technique and advanced manufacturing technology. To deal with more errors, LDPC codes show superior performance to conventional BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chip memory cost and high-throughput demand. This paper presents a byte-reconfigurable cost-effective high-throughput QC-LDPC codec design for NAND Flash memory systems. Reconfigurable codec design is proposed to support various QC-LDPC codes for different Flash memories. To save on-chip memory cost, shared-memory architecture and rescheduling architecture are presented for encoder and decoder, respectively. The shared-memory architecture can save 23% area cost of the encoder and the rescheduling architecture reduces 15% area cost of decoder. In addition, the proposed sub-iteration based early termination (SIB-ET) scheme reduces 29.6% decoding iteration counts compare with the state-of-the-art early termination scheme when raw BER of Flash memory is 3×10-3 . Finally, the QC-LDPC codec for NAND Flash memory systems is implemented in TSMC 90 nm technology. The post-layout result shows that the core size is only 6.72 mm2 at 222 MHz operating frequency.
EXISTING SYSTEM :
? These mechanisms are collectively known as data path protection, and protect against errors that can be introduced by the various SRAM and DRAM structures that exist within the SSD.
? When the ECC correction capability is exceeded, the SSD controller is unable to count how many errors exist in the raw data.
? When no external voltage is applied to any of the electrodes (i.e., CG, source, and drain) of a flash cell, an electric field still exists between the FG and the substrate, generated by the charge present in the FG.
? We believe similar (yet likely more difficult to exploit) vulnerabilities exist in MLC NAND flash memory as well, as described in recent work from our research group.
DISADVANTAGE :
? Low-density parity-check (LDPC) codes with soft-decision have been proposed as ECC to solve the reliability issues of NAND Flash memory.
? ECC design is emerging as a critical issue in SSDs. Nowadays, NAND Flash-based systems heavily rely on BCH codes to tolerate RBER.
? If data are not overwritten within their retention guarantee, background writes with normal write speed are issued.
? The main issue with this design is since every write needs to be encoded in LDPC, a high-throughput LDPC encoder is required to prevent the LDPC encoder from being the bottleneck.
PROPOSED SYSTEM :
• In this paper, we propose two variable-rate encoder architecture designs, targeted to specific applications and offering unique advantages.
• A wireless communication system, where it is possible to decide the code rate before transmission according to the SNR of the channel, and a memory system, where the bit-error-rate increases with lifetime of the memory, are the two targeted applications of the proposed designs.
• The proposed architecture can be employed to encode different portions of the data-stream with different rates.
• In this paper, we propose two efficient encoding hardware designs for reconfigurable IRA-LDPC codes that can be used for such systems.
ADVANTAGE :
? It can be observed that performance of QC-LDPC code is better than BCH code with the same code rate.
? Although implemented early termination in the decoder, the parity-check operation only performs at the end of iteration, which is not efficient enough.
? Nand Flash memory, one of prevailing of non-volatile memory systems (NVMS), is widely used in many consumer electronic products.
? BCH codes are widely used to perform ECC functions of Flash memory.
? The codeword length of LDPC codes for Flash memory system is used to be multiple KBs.
? However, there is still a room for improvement in performance and area efficiency in these designs.
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