An Efficient Constant Multiplier Architecture Based on Vertical Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
Abstract : This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coeffi- cients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.
? The existing system based on 2 and 3 bit BCSE algorithm that expresses multiplying the input (X) and the coefficient (H) partial products are generated and each bit is allowed through 4:1 multiplexers and addition shift operation takes place.
? 3-bit BCSE algorithm is a method of assigning the values that existing in the sequence by leaving the upcoming three bits of each bit.
? The convention considered for representing the input and the coefficient of the earlier designed FIR filter has signed magnitude format also gives a scope to modify the data representation to signed decimal number for wider applicability of the proposed FIR filter in any systems.
? Designing a FIR filter consisting of coefficients with positive signed high values also has the same problem.
? In higher order and lower order filters, there are a large number of small valued negative coefficients and higher valued positive coefficients respectively, which create the high area and power consumption problem during their hardware implementation.
? This problem has occurred as 2-bit or 3-bit BCSs have been applied vertically only in the first layer of MATs according to the earlier proposed fixed-bit BCSE algorithms.
? Our proposed technique can solve the problem of high power and area consumption problem for both the cases, viz. small valued negative coefficient and high valued positive coefficient.
• Vertical and horizontal BCSEs are the two types of BCSE used for eliminating the BCSs present across the adjacent coefficients and within the coefficients respectively in any BCSE method.
• However, this paper proposes one new BCSE algorithm which is a combination of vertical and horizontal BCSE for designing an efficient reconfigurable FIR filter.
• By using this proposed algorithm number of multiplexer used will be less. multiplier switching activities get reduced in our proposed algorithm, a 2-bit vertical BCSE has been applied first on the adjacent coefficient, followed by 4-bit and 8-bit horizontal BCSEs to detect and eliminate as many BCSs as possible which are present within each of the coefficient.
? In any FIR filter, the multiplier is the major constraint which defines the performance of the desired filter.
? The coefficients are generated using MATLAB FDA tool and the performance measures viz. speed, power and area of each of these filters have been calculated by using Synopsys design compiler EDA tool along with Faraday 90 nm technology library.
? In FIR filter, the multiplication operation is performed between one particular variable (the input) and many constants (the coefficients) and known as the multiple constant multiplication (MCM).
? Some techniques have been introduced for efficient reconfigurable constant multiplier design for any application where the filter's coefficients are changing in real time e.g. multi-standard digital up/down converter.
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