An ADPLL based PSK Receiver for VHBR 13.56 MHz Contactless Smartcards and NFC Applications
Abstract : This paper proposes an all-digital phase-locked loop (ADPLL) used as the phase-shift keying (PSK) receiver for very high bit rate (VHBR) of 13.56 MHz smartcards. A detailed implementation from system to circuit level is presented. This ADPLL-based PSK demodulator mainly consists of a high dynamic range time to digital converter (TDC) without pulse shrinking effect, a dual-path digital loop filter (DLF), and a fine resolution digital controlled oscillator (DCO) based on capacitor division without dithering. This design is fabricated by GF CMOS 40 nm technology with a core area of only 0.035 mm2 . The A for?measurement results show low current consumption of 40 A for PSK demodulation with 1.2 V?phase locking and 70 supply. Both integral non-linearity (INL) and differential nonlinearity (DNL) of our TDC are smaller than 0.6 LSB. This prototype can demodulate 8-PSK at a symbol rate of 6.78 MHz, corresponding to a data rate of 20.34 Mbps, with an energy efficiency of 4.1 pJ/bit.
? Near Field Communication (NFC) is a new, short-range wireless connectivity technology that evolved from a combination of existing contactless identification and interconnection technologies.
? The NFC device behaves like an existing contactless card conforming to one of the legacy standards.
? NFC is intended to be used as an access key to contents and for services such as cashless payment, ticketing and access control.
? The NFC forum develops specifications which ensure interoperability of NFC units and services.
? To ensure interoperability between mobile phones and RFID chip cards of different manufacturers, digital protocol tests and RF measurements are required on NFC devices.
? Although the pad pattern design suggested above might help in eliminating some of the surface mounting problems, special considerations are needed in the stencil design and the paste printing for both the perimeter and the thermal pads.
? In most applications, the QFNs will be mounted on smaller, thinner, and denser PCBs that introduce further challenges due to the handling and the heating issues.
? It should also be noted that voids in the thermal pad region do not impact the reliability of the perimeter solder joints.
? The fillet formation is also a function of the PCB land size, the printed solder volume, and the package standoff height.
• Any PICC antenna falling within the “Class 1” dimensions is considered an ID-1 antenna for the purpose of this specification.
• It should be emphasized that this is just a guideline to help the user in developing the proper board design and surface mount process.
• Actual studies as well as development effort maybe needed to optimize the process as per user's surface mount practices and requirements.
• There are different methods employed within the industry for this purpose, such as “via tenting” (from the top or bottom side) using dry film solder mask, “via plugging” with liquid photoimagible (LPI) solder mask from the bottom side, or “via encroaching”.
? This design shows advantageous jitter and power performance as well as area efficiency
? Some works have very attractive performance, such as achieving 2-cycle lock-in, but it has relatively large current consumption.
? However, their area and energy efficiency may not be satisfactory, and it also shows very little scalability to advanced technology node.
? This paper proposes a power and area efficient ADPLL implementation for contactless VHBR PSK demodulation.
? The proposed capacitance division method results in good phase noise without dithering, and enables this work to achieve the best energy efficiency of 4.1 pJ/bit.
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