Antiwear Leveling Design for SSDs With Hybrid ECC Capability
Abstract : With the joint considerations of reliability and performance, hybrid error correction code (ECC) becomes an option in the designs of solid-state drives (SSDs). Unfortunately, wear leveling (WL) might result in the early performance degradation to SSDs, which is common with a limited number of P/E cycles, due to the efforts to delay the bit-error-rate growth. In this paper, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability. The capability of the proposed design was evaluated by a series of experiments, for which it was shown that the proposed design could greatly improve the read and write performance of SSDs up to 50% without affecting the endurance of the investigated SSDs, compared with traditional approaches.
? In this article, we target SSDs that adopt an overlong ECC for all user data (not just for some specific flash pages/blocks).
? Among existing schemes, Cross-Page and PG Decoupling are applicable to general SSDs, but their read performance is poor.
? Some existing works have also studied the read performance degradation due to flash reliability issues.
? We group ECC residues of logically consecutive data pages into ECC pages, caching ECC pages can exploit the spatial locality that commonly exists in real-world workloads.
? That SCORE achieves significant read performance improvements under various workloads, compared to existing schemes.
? The problem is even exacerbated, due to the programming scheme and data encoding, when more than one page share Flash cells in many MLC chip designs.
? In particular, an anti-WL design is proposed to avoid such a performance problem so that the performance of SSDs with hybrid ECC capability can be improved without sacrificing their reliability.
? This problem will become more serious while the hybrid ECC is adopted in the SSD design.
? Many excellent FTL designs have been proposed to resolve the management issues of Flash memory.
• We propose a novel scheme to efficiently cache overlong ECCs, called SCORE, to improve the SSD performance.
• Our proposed design is applicable to either BCH codes or LDPC codes as long as the ECC unit size exceeds the spare area limit.
• Some designs were proposed to store ECC residues in dedicated high-speed non-volatile storage medium, such as SLC flash and phase change memory (PCM).
• In this article, we propose SCORE to improve the SSD performance by caching the overlong ECC.
• These caches adopt the least recently used (LRU) replacement policy with full associativity for simplicity and demonstration purpose (other advanced policies can also be adopted).
? This design is also different from those works that improve performance with WL schemes to avoid the fast-increasing BER, because WL will quick exhaust the BCH lifespan of blocks and result in the degradation of system performance.
? It has been an active area in the exploring of better ECC technology to optimize the reliability, performance, and capacity of SSDs.
? Our design can not only provide better performance by hiding the overheads of LDPC but also guarantee the device lifetime with the isolation of hot/cold data.
? When the RBER of a block is low, the proposed hybrid ECC uses the BCH mode as its default ECC so as to achieve better read/write performance.
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