An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2^k, 2^p-1}
ABSTARCT :
The application of residue number system (RNS) to digital signal processing lies in the ability to operate on signed numbers. However, the available RNS-to-binary (reverse) converters have been designed for unsigned numbers, which means that they do not produce signed outputs. Usually, some additional circuits are introduced at the output of the reverse converter to map the unsigned generated output into a signed number representation. This paper proposes a novel method to design reverse converters with signed output for a class of RNS moduli sets of composite form {2k, 2P - 1}. The structure of the modulo adder used in the last stage of the proposed converters is modified in order to reuse the internal circuits to produce the signed output. This adder component is especially designed for achieving reverse converters with signed output, imposing very low area and delay overheads compared with unsigned converters. The proposed approach is applied to design reverse converters for different moduli sets and to implement application specific integrated circuits. Experimental results show that for a 4-moduli converter, the proposed design can outperform the traditional method to obtain signed outputs by improving the delay, chip-area, and energy consumption by up to 9%, 21%, and 35%, respectively.
EXISTING SYSTEM :
? This independency reduces the time needed to perform residue-based arithmetic operations compared with binarybased operations.
? Therefore, RNS is used efficiently in some digital signal processing and cryptographic applications that require highspeed computations.
? The moduli set selection is determined by the dynamic range, the number of moduli, and the form of moduli targeted.
? While some applications can be well served by a three-moduli set, other applications require a wider dynamic range, a higher level of parallelism, and moduli forms that ease the residue-to-binary conversion and arithmetic operations within any RNS-based processor.
DISADVANTAGE :
? This work is the first attempt in the RNS literature that tackles the specific problem of integrating the signed number representation on the RNS reverse converters.
? The proposed approach tackles this problem by reusing the internal circuits of the final modulo adder of any reverse converter for the c-class moduli sets.
? This issue has motivated the investigation of alternative number systems such as the residue number systems (RNS).
? The RCA architecture is more suitable for embedded systems applications where low area and power consumption are key issues; whereas fast adders, such as those with parallel-prefix architectures are more suitable for real-time systems with critical timing constraints.
PROPOSED SYSTEM :
• We propose a method to design reverse converters by decomposing the original moduli set and applying the MRC.
• In order to experimentally evaluate the practical interest of the proposed converters, not only these converters but also the ones presented in were implemented.
• The penalty in the area forced by the proposed converter is not as pronounced as theoretically expected.
• The proposed converter includes parallel computation flows, the synthesis tool can further optimize the resource usage on the flows that are not in the critical path, which benefits the proposed converter regarding area.
ADVANTAGE :
? The design of efficient reverse converters has been a significant field of research in order to mitigate the impact of this component on the general performance of the RNS-based systems.
? The efficiency of the proposed adder component, which is used to transform unsigned reverse converters to signed reverse converters, with a low overhead on performance, cost, and energy consumption.
? The proposed signed design has considerably better performance than the traditional signed architecture, and the imposed delay overhead relatively to the original unsigned design is low.
? This is mainly due to the fact that the weight of the last modulo adder inthe performance of the 5-moduli converter is lower than that for the 4-moduli converter.
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