An Efficient Fault Tolerance Design for Integer Parallel Matrix Vector Multiplication
Abstract : Parallel matrix processing is a typical operation in many systems, and in particular matrix–vector multiplication (MVM) is one of the most common operations in the modern digital signal processing and digital communication systems. This paper proposes a faulttolerant design for integer parallel MVMs. The scheme combines ideas from error correction codes with the self-checking capability of MVM. Field-programmable gate array evaluation shows that the proposed scheme can significantly reduce the overheads compared to the protection of each MVM on its own. Therefore, the proposed technique can be used to reduce the cost of providing fault tolerance in practical implementations.
? There are distinct techniques exist to achieve fault tolerance.
? Modification at the implementation level of style by the insertion of a brand new technology will usually build viable an existing marginal algorithmic rule or design.
? There are distinct techniques exist to achieve fault tolerance. The most used technique is algorithmic-primarily based fault tolerance (ABFT) techniques that attempt to use recursive properties to find and accurate errors.
? Existing algorithm-based fault tolerance approaches for sparse matrix operations detect and correct errors, but they often rely on expensive error localization steps.
? Electronic circuits are progressively appearing in automotive, medical and space applications wherever reliability is essential.
? Digital filters are one in all the foremost normally used signal process circuits and a number of other techniques are planned protect them from errors.
? Parallel processing with error correction has provided fast processing with fault tolerance capabilities.
? It is flexible in the sense that it can be applied on wide range of problem sizes, and that its performance can be controlled through a small set of tuning parameters.
• Field-programmable entryway exhibit assessment shows that the proposed plan can fundamentally decrease the overheads contrasted with the security of each MVM all alone.
• In this way, the proposed strategy can be utilized to lessen the expense of giving adaptation to internal failure in down to earth usage.
• FPGA-based assessment shows that the proposed plan can lessen the overhead required by up to 20% and 40% contrasted with discrete assurance, for 4 and 8 equal MVMs, separately.
• There has been a number of parallel multiplication approaches proposed to speed up computation.
? With increasing demand for high performance or throughput, parallel computing is becoming more important in high-performance computing systems, cloud computing systems, and communication systems.
? Parallel matrix processing with a common input vector (parallel MVMs) is performed for precoding in multiuser multi-in multi-out (MIMO) (especially large-scale MIMO)and high-performance low density parity check decoders.
? The scheme is based on considering each filter as a bit in an error correction code (ECC) so that parity check filters are added and used to detect and correct errors.
? The row checksum does not exist for an input vector, such ABFT scheme can only be used for error detection in MVM.
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