Design of Power and Area Efficient Approximate Multipliers
Abstract : Approximate computing can decrease the design complexity with an increase in performance and power efficiency for error resilient applications. This brief deals with a new design approach for approximation of multipliers. The partial products of the multiplier are altered to introduce varying probability terms. Logic complexity of approximation is varied for the accumulation of altered partial products based on their probability. The proposed approximation is utilized in two variants of 16-bit multipliers. Synthesis results reveal that two proposed multipliers achieve power savings of 72% and 38%, respectively, compared to an exact multiplier. They have better precision when compared to existing approximate multipliers. Mean relative error figures are as low as 7.6% and 0.02% for the proposed approximate multipliers, which are better than the previous works. Performance of the proposed multipliers is evaluated with an image processing application, where one of the proposed models achieves the highest peak signal to noise ratio.
? A 8-bit unsigned1 number is employed for illustration to explain the projected methodology in approximation of multipliers.
? That situation is a search engine where no accurate answer may exist for a particular search query and hence, lot of answers may be suitable.
? They have better precision when compared to existing approximate multipliers.
? The projected approximate technique is applied to signed multiplication together with Booth multipliers likewise, except it's not applied to sign extension bits.
? These factors square measure thought-about, whereas applying approximation to the altered partial product matrix.
? The major drawback of the proposed compressors is that they give nonzero output for zero valued inputs, which largely affects the mean relative error (MRE).
? Exact multiplier is voltage scaled from 1 to 0.85 V (VOS), and its impact on energy consumption and image quality is computed.
? As the switching activity impacts most significant part of the design in VOS, PSNR values are affected.
? The approximate design proposed in this brief overcomes the existing drawback. This leads to better precision.
• In, static segment multiplier is proposed where selected segment of input operands are multiplied instead of whole. Voltage over scaling effect with delay of the circuit is used for approximation in where power is reduced with timing violation.
• In this paper, the proposed approximate multiplier uses propagate and generate signals which are modified from the partial products.
• Due to higher probability of 1/4 and 7/16 for normal partial product and propagate signals approximate half adder, full adder and 4:2 compressor is used for the accumulation purpose.
• The decade, several research efforts have explored approximate computing throughout all the layers of computing stack, however, most of the work at hardware level of abstraction has been proposed on adders.
? The intensity of image-1 being mostly on the lower end of the histogram causes poor performance of ACM multipliers.
? In, inaccurate counter design has been proposed for use in power efficient Wallace tree multiplier.
? The efficiency of the proposed multipliers is compared with existing approximate multipliers.
? In, two designs of approximate 4-2 compressors are presented and used in partial product reduction tree of four variants of 8 × 8 Dadda multiplier.
? To propose efficient approximate multipliers, partial products of the multiplier are modified using generate and propagate signals.
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