A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage
ABSTARCT :
This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in offset pulse and an offset pulsewidth detection schemes. With several techniques, including a built-in coarse gain calibration mechanism, the proposed TS architecture overcomes a nonlinearity due to the signal propagation and gain mismatch between coarse and fine stages. The simulation results of the TDC implemented in a 0.18-µm standard CMOS technology demonstrate 2.0-ps resolution and 16-bit range that corresponds to ~130-ns input time interval with 0.08-mm2 area. It operates at 3.3 MS/s with 18.0 mW from 1.8-V supply and achieves 1.44-ps single-shot precision.
EXISTING SYSTEM :
? The most popular temperature sensors used today are the thermocouple, resistive temperature device (RTD), thermistor and integrated silicon-based sensors.
? However, if we exclude the 4 types of temperature estimation functions which are not dependent of the temperature at all, there exist only 12 types of temperature estimation functions.
? The mismatch problem between fine delay cells distributed over large die area still exists.
? In, the implemented time domain CMOS temperature sensor shows the temperature resolution of 0.1 °C, the temperature error of -0.4 °C to +0.6 °C over the temperature range from 0 °C to 90 °C, and the very large die area of 0.6 mm2.
DISADVANTAGE :
? It also alleviates the mismatch issue because both rising and falling transitions propagate the same way on the layout.
? In this paper, in order to achieve a fine resolution and wide range at the same time, we employ a sub-gate-delay resolution PS architecture as the fine TDC of the TS architecture and propose several techniques to overcome the issues in the conventional PS and TS TDCs discussed so far.
? The transistor size and the current consumption of the inverters in PSB have to be carefully chosen because the impact of jitter accumulation and process variation needs to be considered.
PROPOSED SYSTEM :
• In this paper, two novel voltage-to-time converters are proposed at which the input voltage signal is connected to the body terminal of the starving transistor rather than its gate terminal.
• A fully digital time-based ADC is proposed to reduce the chip area at which the power consumption is reduced to 380 µW but still relatively high.
• There is no need for any continuous-time (CT) comparator or reference generator as the proposed ADC shifts the conventional voltage-domain level crossing to the phase domain.
• This proposed ADC operates at high sampling frequency of 4 GHz.
ADVANTAGE :
? In particular, with the recent improvement in TDC performance, it is often used in high-precision time-of-flight measurement applications, such as laser range finder and mass spectrometry.
? The TDC determines the overall performance of the measurement, a few ps time resolution with low jitter at a sampling rate of several MS/s is often requested.
? Though the conventional PS TDC can be used with a fixed offset pulsewidth to keep the input pulse sufficiently wide to accept the fine time difference, it wastes time and power to wait for the conversion of the offset part and it also integrates extra jitter.
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