Source Code Error Detection in High-Level Synthesis Functional Verification

Abstract : A dynamic functional verification method that compares untimed simulations versus timed simulations for synthesizable [high-level synthesis (HLS)] behavioral descriptions (ANSI-C) is presented in this paper. This paper proposes a method that automatically inserts a set of probes into the untimed behavioral description. These probes record the status of internal signals of the behavioral description during an initial untimed simulation. These simulation results are subsequently used as golden outputs for the verification of the internal signals during a timed simulation once the behavioral description has been synthesized using HLS. Our proposed method reports any simulation mismatches and accurately pinpoints any discrepancies between the functional Software (SW) simulation and the timed simulation at the original behavioral description (source code). Our method does not only determine where to place the probes, but is also able to insert different type of probes based on the specified HLS synthesis options in order not to interfere with the HLS process, minimizing the total number of probes and the size of the data to be stored in the trace file in order to minimize the running time. Results show that our proposed method is very effective and extremely simple to use as it is fully automated.
 EXISTING SYSTEM :
 ? The paper is organised in a section wise according to continue the process of improving the performances of the proposed system than the existing system. ? The existing system of serial shift register, Parallel shift registers are introduced. ? Paralleled designed shift register use highly low power compared to the existing techniques of the low power devices. ? Double modular technique is used to overcome from the feedback usage of the registers for the safer operations. ? The simulation of the proposed circuit is performed and evaluated the performance to show the better performance than the existing.
 DISADVANTAGE :
 ? The main problem is that these test vectors only cover the inputs and outputs of the behavioral description. ? The main problem with this approach is when the behavioral description includes arrays and loops, which are extremely common in high-level language descriptions. ? The second problem is that the additions interfere with the HLS and hence the resultant synthesized circuit will not have the same timing behavior as the original one (the overall latency will increase). ? The problem in this code is that both, lefty and righty signals, were declared as unsigned integers.
 PROPOSED SYSTEM :
 • In the proposed methods with the new algorithm of Hamming codes triple modular techniques are employed. • The proposed scheme results are given as lower bound and asymptotic expression based on an accurate upper bound of the end-to-endSignal-to-Noise Ratio (SNR). • It is demonstrate that the proposed system has the same asymptotic BER performance and an effectual throughput evaluated with the conventional bidirectional relay system based on four transmission phases and the proposed scheme is efficient for practical wireless communication. • In this proposed system, a new way is presented by optimizing the hamming code to detect and correct the errors.
 ADVANTAGE :
 ? The HLS tool often duplicates signals for performance issues and often removes others, which makes it often difficult to trace any signals back to the original source code. ? In this paper, we address the issue of how to efficiently verify the functionality between an original untimed SW behavioral description and the synthesized design after behavioral synthesis. ? The designer also refines the data types in order to obtain the smallest possible and most efficient HW design. ? This technology library is used by every HLS tool to efficiently schedule the behavioral description and contains the area and delay of all basic operators for different bitwidths.

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